Datasheet

1266
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
46.11.2 Post Processor Device Configuration Register
Name: VDEC_PPCR
Access: Read-write
• MAX_BURST_LEN: Maximum burst length for post-processor bus transactions
Valid values for AHB are 0, 1, 4, 8 and 16.
0: AHB INCR transfer type is used always.
1: AHB SINGLE transfer type is used always.
4, 8, 16: Set AHB maximum burst length to INCR4, INCR8 or INCR16. Also INCR and SINGLE types are allowed.
• PPO_LE: Post-processor Output Endian Mode (for Y Cb Cr)
0: Big endian
1: Little endian
For 16-bit RGB data, this bit woks as a pixel swapping bit.
• PPI_LE: Post-processor Input Endian Mode
0: Big endian
1: Little endian
• PPDCGE: Post-processor Dynamic Clock Gating Enable
0: Clock is running for all post-processor structures.
1: Clock is gated for post-processor structures that are not used.
Clock gating value should be changed only when the post-processor is disabled.
• AHB_BURST: AHB precise burst and data discard enable
0: INCR bursts of undefined length 2 or 3 may be issued when necessary.
1: Only the precise AHB bursts (SINGLE, INCR4, INCR8 and INCR16) are used in SDRAM read accesses. Extra data is
discarded internally.
• HLOCK: HLOCK enable
0: Locked transfers disabled.
1: Locked transfers enabled.
When a locked transfer is granted, bus grant cannot be lost even if a higher priority master requests the bus.
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15 14 13 12 11 10 9 8
HLOCK–––––AHB_BURSTPPDCGE
76543210
PPI_LE PPO_LE – MAX_BURST_LEN