Datasheet

1005
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
43.4 Pin Name List
The AC97 reset signal provided to the primary codec can be generated by a PIO.
43.5 Application Block Diagram
Figure 43-2. Application Block diagram
Table 43-1. I/O Lines Description
Pin Name Pin Description Type
AC97CK 12.288-MHz bit-rate clock Input
AC97RX Receiver Data (Referred as SDATA_IN in AC-link spec) Input
AC97FS 48-KHz frame indicator and synchronizer Output
AC97TX Transmitter Data (Referred as SDATA_OUT in AC-link spec) Output
AC 97 Controller
AC97TX
AC97RX
PIOx
AC'97 Primary Codec
AC97FS
AC97CK
AC97_RESET
AC97_SYNC
AC97_SDATA_OUT
AC97_BITCLK
AC-link
AC97_SDATA_IN