Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsDev KitsPCB design board

6355F–ATARM–12-Mar-13

Description

The SAM9M10 is a multimedia enabled mid-range ARM926-based embedded MPU run-

ning at 400MHz, combining user interfaces, video playback and connectivity. It includes

hardware video decoder, LCD Controller, resistive touchscreen, camera interface, audio,

Ethernet 10/100 and high speed USB and SDIO.

The hardware video decoder supports H.264, MPEG-4, MPEG-2, VC-1, H.263. The

SAM9M10 also provides hardware image post-processing, such as image scaling, color

conversion and image rotation.

The SAM9M10 supports the latest generation of DDR2 and NAND Flash memory inter-

faces for program and data storage. An internal 133 MHz multi-layer bus architecture

associated with 37 DMA channels, a dual external bus interface and distributed memory

including a 64-KByte SRAM which can be configured as a tightly coupled memory (TCM)

sustains the high bandwidth required by the processor and the high speed peripherals.

The I/Os support 1.8V or 3.3V operation, which are independently configurable for the

memory interface and peripheral I/Os. This feature completely eliminates the need for any

external level shifters. In addition it supports 0.8 ball pitch package for low cost PCB

manufacturing.

The SAM9M10 power management controller features efficient clock gating and a battery

backup section minimizing power consumption in active and standby modes.

The SAM9M10 device is particularly well suited for media-rich displays and control panels

in home and commercial buildings, POS terminals, entertainment systems, internet appli-

ances and medical.

ARM-based Embedded MPU

SAM9M10

DATASHEET

Summary of content (1361 pages)

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ARM-based Embedded MPU SAM9M10 DATASHEET Description The SAM9M10 is a multimedia enabled mid-range ARM926-based embedded MPU running at 400MHz, combining user interfaces, video playback and connectivity. It includes hardware video decoder, LCD Controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. The hardware video decoder supports H.264, MPEG-4, MPEG-2, VC-1, H.263.
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1.
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PDC DBGU AIC MCI0/MCI1 SD/SDIO CE ATA FIFO TWI0 TWI1 PIOE PIOB PIOC RSTC PIOD POR RTC PIOA POR VDDCORE SHDC RTT 4 GPBR RC OSC 32K PIT WDT OSC12M PLLUTMI PMC PLLA VDDBU NRST XIN32 XOUT32 SHDN WKUP XIN XOUT PLLRCA DRXD DTXD FIQ IRQ PCK0-PCK1 System Controller PIO EL JTA GS NT RS T TD I TD O TM TCS K RT CK PDC USART0 USART1 USART2 USART3 ROM 64KB SRAM 64KB 4-CH PWM I TC0 TC1 TC2 D DCache ICache MMU 32Kbytes 32K bytes Bus Interface ITCM DTCM ARM926EJ-S In-Circuit Emul
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3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Name Signal Description List Function Type Active Level Reference Voltage Comments Power Supplies VDDIOM0 DDR2 I/O Lines Power Supply Power 1.65V to 1.95V VDDIOM1 EBI I/O Lines Power Supply Power 1.65V to 1.95V or 3.0V to3.6V VDDIOP0 Peripherals I/O Lines Power Supply Power 1.65V to 3.6V VDDIOP1 Peripherals I/O Lines Power Supply Power 1.65V to 3.
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Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Reference Voltage Comments Shutdown, Wakeup Logic SHDN Shut-Down Control Output VDDBU Driven at 0V only. 0: The device is in backup mode 1: The device is running (not in backup mode). WKUP Wake-Up Input Input VDDBU Accept between 0V and VDDBU.
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Table 3-1.
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Table 3-1.
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Table 3-1.
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Table 3-1.
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Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Reference Voltage GPAD4-GPAD7 Analog Inputs Analog VDDANA TSADTRG ADC Trigger Input VDDANA TSADVREF ADC Reference Analog VDDANA Notes: Comments 1. Refer to peripheral multiplexing tables in Section 8.4 “Peripheral Signals Multiplexing on I/O Lines” for these signals. 2. When configured as an input, the NRST pin enables asynchronous reset of the device when asserted low.
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4. Package and Pinout The SAM9M10 is delivered in a 324-ball TFBGA package. 4.1 Mechanical Overview of the 324-ball TFBGA Package Figure 4-1 shows the orientation of the 324-ball TFBGA Package Figure 4-1.
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4.2 324-ball TFBGA Package Pinout Table 4-1.
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Table 4-1.
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5. Power Considerations 5.1 Power Supplies The SAM9M10 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V typical. • VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical). • VDDIOM1 pins: Power the External Bus Interface 1 I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V typical).
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6. Memories Figure 6-1.
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6.1 Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects NCS0 to NCS5.
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• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus. • Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters.
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– DDR_D[15] <=> DELAY2[31:28] DDR_A[13:0] controlled by 2 registers, DELAY3 and DELAY4, located in the DDRSDRC user interface – DDR_A[0] <=> DELAY3[3:0], – DDR_A[1] <=> DELAY3[7:4], ..., – DDR_A[6] <=> DELAY3[27:24], – DDR_A[7] <=> DELAY3[31:28] – DDR_A[8] <=> DELAY4[3:0], – DDR_A[9] <=> DELAY4[7:4], ...
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– A[17] <=> DELAY7[7:4], – A[18] <=> DELAY7[11:8] A25 on PC[12] and A[24:19] on PC[7:2] – A19 <=> DELAY7[15:12], – A20 <=> DELAY7[19:16],..., – A23 <=> DELAY7[31:28], – A24 <=> DELAY8[3:0], – A25 <=> DELAY8[7:4] • PIOA User interface The delay can only be inserted on the HSMCI0 and HSMCI1 I/O lines, so on PA[9:2] and PA[30:23]. The delay is controlled by 2 registers, DELAY1 and DELAY2, located in the PIOA user interface. – PA[2] <=> DELAY1[3:0], – PA[3] <=> DELAY1[7:4],...
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7.2 System Controller Block Diagram Figure 7-1. SAM9M10 System Controller Block Diagram System Controller VDDCORE Powered irq0-irq2 fiq periph_irq[2..
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7.3 Chip Identification The SAM9M10 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register. • Chip ID: 0x819B05A2 • Ext ID: 0x00000002 • JTAG ID: 05B2_703F • ARM926 TAP ID: 0x0792603F 7.4 Backup Section The SAM9M10 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • SCKR register • RTT • RTC • Shutdown Controller • 4 backup registers • A part of RSTC This section is powered by the VDDBU rail.
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8. Peripherals 8.1 Peripheral Mapping As shown in Figure 6.1, the Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space. 8.2 Peripheral Identifiers Table 8-1 defines the Peripheral Identifiers of the SAM9M10.
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8.3 Peripheral Interrupts and Clock Control 8.3.1 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the DDR2/LPDDR Controller • the Debug Unit • the Periodic Interval Timer • the Real-Time Timer • the Real-Time Clock • the Watchdog Timer • the Reset Controller • the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 8.3.
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8.4.1 Table 8-2.
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8.4.2 Table 8-3.
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8.4.3 Table 8-4.
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8.4.4 Table 8-5.
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8.4.5 Table 8-6.
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9. ARM926EJ-S Processor Overview 9.1 Description The ARM926EJ-S™ processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density.
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9.
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9.3 Block Diagram Figure 9-1. ARM926EJ-S Internal Functional Block Diagram CP15 System Configuration Coprocessor External Coprocessors ETM9 External Coprocessor Interface Trace Port Interface Write Data ARM9EJ-S Processor Core Instruction Fetches Read Data Data Address Instruction Address MMU DTCM Interface Data TLB Instruction TLB ITCM Interface Data TCM Instruction TCM Instruction Address Data Address Data Cache AHB Interface and Write Buffer Instruction Cache AMBA AHB 9.
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• ARM state: 32-bit, word-aligned ARM instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 9.4.
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• Fast Interrupt (FIQ) mode is used for handling fast interrupts.
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The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed.
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Figure 9-2.
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Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. 9.4.7.
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ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). For further details, see the ARM Technical Reference Manual. Table 9-2 gives the ARM instruction mnemonic list. Table 9-2.
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9.4.9 New ARM Instruction Set . Table 9-3.
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Table 9-4.
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9.5 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ARM9EJ-S • Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 9-5. Table 9-5.
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9.5.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
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9.6 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, Windows CE®, and Linux®. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13.
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9.6.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access.
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9.7 Caches and Write Buffer The ARM926EJ-S contains a 32K Byte Instruction Cache (ICache), a 32K Byte Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache.
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The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 9.7.2.
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9.8.3 TCM Mapping The TCMs can be located anywhere in the memory map, with a single region available for ITCM and a separate region available for DTCM. The TCMs are physically addressed and can be placed anywhere in physical address space. However, the base address of a TCM must be aligned to its size, and the DTCM and ITCM regions must not overlap. TCM mapping is performed by using TCM region register (register 9) in CP15. The user should input the right mapping address for TCMs. 9.
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10. SAM9M10 Debug and Test 10.1 Description The SAM9M10 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel.
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Block Diagram Figure 10-1. Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP Boundary Port JTAGSEL TDO RTCK POR Reset and Test ARM9EJ-S TST ICE-RT ARM926EJ-S DTXD PDC DBGU PIO 10.
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10.4 Application Examples 10.4.1 Debug Environment Figure 10-2 on page 49 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 10-2.
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10.4.2 Test Environment Figure 10-3 on page 50 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 10-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Chip n SAM9M10 Chip 2 Chip 1 SAM9M10-based Application Board In Test 10.5 Debug and Test Pin Description Table 10-1.
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10.6 Functional Description 10.6.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 10.6.2 EmbeddedICE The ARM9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface.
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The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The SAM9M10 Debug Unit Chip ID value is 0x819B 05A2 and the extended ID is 0x00000002 on 32-bit width.
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11. Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities the memory layout can be changed with two parameters. • REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. This is done by software once the system has boot. • BMS allows the user to layout to 0x0, when convenient, the ROM or an external memory. This is done by hardware at reset.
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11.2 Flow Diagram The Boot Program implements the algorithm shown below in Figure 11-1. Figure 11-1.
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11.3 Device Initialization 11.3.1 Clock at Start Up At boot start up, the processor clock (PCK) and the master clock (MCK) are found on the slow clock. The slow clock can be an external 32 kHz crystal oscillator or the internal RC oscillator. By default the slow clock is the internal RC oscillator. Its frequency is not precise and is between 20 kHz and 40 kHz. Its start up is much faster than an external 32 kHz quartz.
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11.4 11.4.1 NVM Boot NVM Bootloader Program Description Figure 11-2. NVM bootloader program diagram Start Initialize NVM Initialization OK No Restore the reset values for the peripherals and Jump to next boot solution Yes Valid code detection in NVM NVM contains valid code No Yes Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals.
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Figure 11-3. Remap Action after Download Completion 0x0000_0000 0x0000_0000 REMAP nternal M nternal S AM 0x0030_0000 0x0030_0000 Internal SRAM Internal SRAM 0x0040_0000 0x0040_0000 Internal ROM Internal ROM The NVM bootloader program initializes the NVM. It initializes the required PIO. It sets the right peripheral depending on the NVM and tries to access the memory.
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Load PC with PC relative addressing instruction: – Rn = Rd = PC = 0xF – I==0 (12-bit immediate value) – P==1 (pre-indexed) – U offset added (U==1) or subtracted (U==0) – W==1 The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his/her own vector. This information is described below. Figure 11-6. Structure of the ARM Vector 6 31 0 Size of the code to download in bytes The value has to be smaller than 60 KBytes.
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11.4.3 NVM Bootloader Sequence Figure 11-7. NVM Bootloader Sequence Diagram Device Setup NAND Flash Boot Yes Copy from NAND Flash to SRAM Run NAND Flash Bootloader Yes Copy from SD Card to SRAM Run SD Card Bootloader Yes Copy from SPI Flash to SRAM Run SPI Flash Bootloader Yes Copy from TWI EEPROM to SRAM Run TWI EEPROM Bootloader No SD Card Boot No SPI Flash Boot No TWI EEPROM Boot No SAM-BA Monitor 11.4.3.1 NAND Flash Boot The NAND Flash bootloader program uses the EBI CS3.
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Supported NAND Flash Devices The supported SLC small block NAND Flash devices that are described below inTable 11-1. Table 11-1. Supported SLC Small Block NAND Flash Size (MBytes) PageSize (Bytes) BlockSsize (Bytes) Bus Width Voltage (V) 0x6E 1 256 4096 8 5 0x64 2 256 4096 8 5 0x6B 4 512 8196 8 5 0xE8 1 256 4096 8 3.3 0xEC 1 256 4096 8 3.3 0xEA 2 256 4096 8 3.3 0xE3 4 512 8196 8 3.3 0xE5 4 512 8196 8 3.3 0xD6 8 512 8196 8 3.
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The SPI Flash bootloader tries to boot on SPI0 Chip Select 0, first looking for SPI Serial flash, and then for SPI DataFlash. It uses only one valid code detection: analysis of ARM exception vectors. The SPI Flash read is done thanks to a Continuous Read command from address 0x0. This command is 0xE8 for DataFlash and 0x0B for Serial Flash devices. Supported DataFlash Devices The SPI Flash Boot program supports all Atmel DataFlash devices. Table 11-2.
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Table 11-3. PIO Driven during Boot Program Execution (Continued) NVM Bootloader Peripheral Pin PIO Line MCI0 MCI0_CK PIOA0 MCI0 MCI0_CD PIOA1 MCI0 MCI0_D0 PIOA2 MCI0 MCI0_D1 PIOA3 MCI0 MCI0_D2 PIOA4 MCI0 MCI0_D3 PIOA5 SPI0 MOSI PIOB1 SPI0 MISO PIOB0 SPI0 SPCK PIOB2 SPI0 NPCS0 PIOB3 TWI0 TWD0 PIOA20 TWI0 TWCK0 PIOA21 DBGU DRXD PIOB12 DBGU DTXD PIOB13 SD Card SPI Flash TWI0 EEPROM SAM-BA Monitor 11.
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Figure 11-8. SAM-BA Monitor Diagram No valid code in NVM Init DBGU and USB No USB Enumeration Successful No Character(s) received on DBGU Yes Run monitor Wait for command on the USB link 11.5.1 Yes Run monitor Wait for command on the DBGU link Command List Table 11-4.
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– Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal following by ‘>’ • Send a file (S): Send a file to a specified address – Address: Address in hexadecimal – Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution.
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Figure 11-9. Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 11.5.3 USB Device Port 11.5.3.1 Supported external crystal / external clocks The only frequency supported by SAM-BA Monitor to allow USB communication is a 12 MHz crystal or external clock. 11.5.3.2 USB class The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB.
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The device also handles some class requests defined in the CDC class. Table 11-6. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 11.5.3.
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12. Reset Controller (RSTC) 12.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 12.2 Embedded Characteristics The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE.
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12.4 Functional Description 12.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • backup_nreset: Affects all the peripherals powered by VDDBU. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin.
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The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 12.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles.
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When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 12-4 shows how the General Reset affects the reset signals. Figure 12-4. General Reset State SLCK Any Freq.
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12.4.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset.
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12.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup.
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12.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
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12.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. • If WDRPROC = 1, only the processor reset is asserted.
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12.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup Reset • Wake-up Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed below: • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated.
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12.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
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12.5 Reset Controller (RSTC) User Interface Table 12-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 Note: Access Reset Backup Reset RSTC_CR Write-only - Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 Mode Register RSTC_MR Read-write - 0x0000_0001 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
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12.5.1 Name: Reset Controller Control Register RSTC_CR Address: 0xFFFFFD00 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect.
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12.5.2 Name: Reset Controller Status Register RSTC_SR Address: 0xFFFFFD04 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
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12.5.3 Name: Reset Controller Mode Register RSTC_MR Address: 0xFFFFFD08 Access: Read-write 31 30 29 28 27 26 25 24 17 – 16 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.
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13. Real-time Timer (RTT) 13.1 Description The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 13.
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The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR.
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13.5 Real-time Timer (RTT) User Interface Table 13-1.
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13.5.1 Name: Real-time Timer Mode Register RTT_MR Address: 0xFFFFFD20 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216.
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13.5.2 Name: Real-time Timer Alarm Register RTT_AR Address: 0xFFFFFD24 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 13.5.
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13.5.4 Name: Real-time Timer Status Register RTT_SR Address: 0xFFFFFD2C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.
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14. Real-time Clock (RTC) 14.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.
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14.4 Product Dependencies 14.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 14.4.2 Interrupt The RTC Interrupt is connected to interrupt source 1 (IRQ1) of the advanced interrupt controller. This interrupt line is due to the OR-wiring of the system peripheral interrupt lines (System Timer, Real Time Clock, Power Management Controller, Memory Controller, etc.).
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14.5.4 Error Checking Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed.
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Figure 14-2.
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14.6 Real Time Clock (RTC) User Interface Table 14-1.
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14.6.1 Name: RTC Control Register RTC_CR Address: 0xFFFFFDB0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters.
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14.6.2 Name: RTC Mode Register RTC_MR Address: 0xFFFFFDB4 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. All non-significant bits read zero.
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14.6.3 Name: RTC Time Register RTC_TIMR Address: 0xFFFFFDB8 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units.
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14.6.4 Name: RTC Calendar Register RTC_CALR Address: 0xFFFFFDBC Access: Read-write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units.
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14.6.5 Name: RTC Time Alarm Register RTC_TIMALR Address: 0xFFFFFDC0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled.
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14.6.6 Name: RTC Calendar Alarm Register RTC_CALALR Address: 0xFFFFFDC4 Access: Read-write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled.
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14.6.7 Name: RTC Status Register RTC_SR Address: 0xFFFFFDC8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. 1 = Time and calendar registers can be updated. • ALARM: Alarm Flag 0 = No alarm matching condition occurred.
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14.6.8 Name: RTC Status Clear Command Register RTC_SCCR Address: 0xFFFFFDCC Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0 = No effect.
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14.6.9 Name: RTC Interrupt Enable Register RTC_IER Address: 0xFFFFFDD0 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect.
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14.6.10 Name: RTC Interrupt Disable Register RTC_IDR Address: 0xFFFFFDD4 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect.
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14.6.11 Name: RTC Interrupt Mask Register RTC_IMR Address: 0xFFFFFDD8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled.
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14.6.12 Name: RTC Valid Entry Register RTC_VER Address: 0xFFFFFDDC Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed.
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SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 104
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15. Periodic Interval Timer (PIT) 15.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Embedded Characteristics • Includes a 20-bit Periodic Counter, with less than 1μs accuracy • Includes a 12-bit Interval Overlay Counter • Real Time OS or Linux/WinCE compliant tick generator 15.3 Block Diagram Figure 15-1.
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15.4 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
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15.5 Periodic Interval Timer (PIT) User Interface Table 15-1.
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15.5.1 Name: Periodic Interval Timer Mode Register PIT_MR Address: 0xFFFFFD30 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 PITIEN 24 PITEN 23 – 22 – 21 – 20 – 19 18 17 16 15 14 13 12 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
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15.5.2 Name: Periodic Interval Timer Status Register PIT_SR Address: 0xFFFFFD34 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS 25 24 17 16 • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
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15.5.4 Name: Periodic Interval Timer Image Register PIT_PIIR Address: 0xFFFFFD3C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
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16. Watchdog Timer (WDT) 16.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.
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16.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
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Figure 16-2.
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16.5 Watchdog Timer (WDT) User Interface Table 16-1.
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16.5.1 Name: Watchdog Timer Control Register WDT_CR Address: 0xFFFFFD40 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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16.5.2 Name: Watchdog Timer Mode Register WDT_MR Address: 0xFFFFFD44 Access: Read-write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 11 22 26 25 24 18 17 16 10 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
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16.5.3 Name: Watchdog Timer Status Register WDT_SR Address: 0xFFFFFD48 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
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SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 118
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17. Shutdown Controller (SHDWC) 17.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 17.2 Embedded Characteristics The Shut Down Controller is supplied on VDDBU and allows a software-controllable shut down of the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the SHDN pin, and thus wakes up the system power supply. 17.3 Block Diagram Figure 17-1.
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17.4 I/O Lines Description Table 17-1. I/O Lines Description Name Description Type WKUP0 Wake-up 0 input Input SHDN Shutdown output Output 17.5 Product Dependencies 17.5.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller. 17.6 Functional Description The Shutdown Controller manages the main power supply.
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17.7 Shutdown Controller (SHDWC) User Interface Table 17-2.
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17.7.1 Name: Shutdown Control Register SHDW_CR Address: 0xFFFFFD10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SHDW • SHDW: Shutdown Command 0 = No effect. 1 = If KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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17.7.2 Name: Shutdown Mode Register SHDW_MR Address: 0xFFFFFD14 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWKEN 16 RTTWKEN 15 14 13 12 11 – 10 – 9 3 – 2 – 1 – 7 6 5 4 CPTWK0 8 – 0 WKMODE0 • WKMODE0: Wake-up Mode 0 WKMODE[1:0] Wake-up Input Transition Selection 0 0 None.
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17.7.3 Name: Shutdown Status Register SHDW_SR Address: 0xFFFFFD18 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWK 16 RTTWK 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WAKEUP0 • WAKEUP0: Wake-up 0 Status 0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
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18. General Purpose Backup Registers (GPBR) 18.1 Description The System Controller embeds Four general-purpose backup registers. 18.2 Embedded Characteristics • Four 32-bit general-purpose backup registers 18.3 General Purpose Backup Registers (GPBR) User Interface Table 18-1. Offset 0x0 ... 0xc Register Mapping Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 3 SYS_GPBR3 Access Reset Read-write – ... ...
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18.3.
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19. Bus Matrix (MATRIX) 19.1 Description The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
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Table 19-1. 19.2.2 List of Bus Matrix Masters150 Master 5 DMA Master 6 ISI Controller DMA Master 7 LCD DMA Master 8 Ethernet MAC DMA Master 9 USB Device High Speed DMA Master 10 USB Host High Speed EHCI DMA Master 11 Video Decoder Matrix Slaves Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed. Table 19-2.
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Figure 19-1. Video Mode Configuration VDEC_SEL Video Decoder LCD + Post Processing DMA DDR_S0 ARM I DDR_S1 ARM I ARM D ARM D VDEC_SEL DDR_S2 MATRIX DDR_S3 Table 19-3.
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. Table 19-4. SAM9M10 Masters to Slaves Access with VDEC_SEL = 1 (default) 4&5 6 7 8 9 10 11 PDC USB HOST OHCI DMA ISI DMA LCD DMA Ethern et MAC USB Device HS USB Host EHCI VDEC X X X X X - X X X - X X X - - - - - X - - UHP OHCI X X - - - - - - - - - UHP EHCI X X - - - - - - - - - LCD User Int.
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At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master. To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave.
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1. Round-Robin Arbitration (default) 2. Fixed Priority Arbitration The resulting algorithm may be complemented by selecting a default master configuration for each slave. When a re-arbitration must be done, specific conditions apply. See Section 19.5.1 “Arbitration Scheduling” on page 132. 19.5.1 Arbitration Scheduling Each arbiter has the ability to arbitrate between two or more different master requests.
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This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). 19.5.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break long accesses, such as back to back undefined length bursts or very long bursts on a very slow slave (e.g., an external low speed memory).
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19.5.2.1 Fixed Priority Arbitration This arbitration algorithm is the first and only applied between masters from distinct priority pools. It is also used inside priority pools other than the highest and lowest ones (intermediate priority pools). It allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user in the MxPR field for each master inside the MATRIX_PRAS and MATRIX_PRBS Priority Registers.
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19.6 Write Protect Registers To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from address offset 0x000 to 0x1FC can be write-protected by setting the WPEN bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR).
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19.7 Bus Matrix (MATRIX) User Interface Table 19-6.
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Table 19-6.
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19.7.1 Name: Bus Matrix Master Configuration Registers MATRIX_MCFG0...MATRIX_MCFG11 Address: 0xFFFFEA00 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 ULBT 0 This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
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19.7.2 Name: Bus Matrix Slave Configuration Registers MATRIX_SCFG0...MATRIX_SCFG7 Address: 0xFFFFEA40 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 20 19 FIXED_DEFMSTR 18 17 16 DEFMSTR_TYPE 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 SLOT_CYCLE 7 6 5 4 3 2 1 0 SLOT_CYCLE This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
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• FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
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19.7.3 Name: Bus Matrix Priority Registers A For Slaves MATRIX_PRAS0...
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19.7.4 Name: Bus Matrix Priority Registers B For Slaves MATRIX_PRBS0...
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19.7.5 Name: Bus Matrix Master Remap Control Register MATRIX_MRCR Address: 0xFFFFEB00 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RCB11 10 RCB10 9 RCB9 8 RCB8 7 RCB7 6 RCB6 5 RCB5 4 RCB4 3 RCB3 2 RCB2 1 RCB1 0 RCB0 This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
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19.7.6 Chip Configuration User Interface Table 19-7.
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19.7.6.
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19.7.6.
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19.7.6.3 Name: EBI Chip Select Assignment Register CCFG_EBICSA Access: Read-write Reset: 0x0007_0000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 DDR_DRIVE 17 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 EBI_DBPUC 7 – 6 – 5 EBI_CS5A 4 EBI_CS4A 3 EBI_CS3A 2 – 1 EBI_CS1A 0 – 16 EBI_DRIVE • EBI_CS1A: EBI Chip Select 1 Assignment 0 = EBI Chip Select 1 is assigned to the Static Memory Controller. 1 = EBI Chip Select 1 is assigned to the SDRAM Controller.
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• DDR_DRIVE: DDR2 dedicated port I/O slew rate selection This allows to avoid overshoots and give the best performances according to the bus load and external memories. 0 = Low Drive, optimized for load capacitance < 30 pF. 1 = High Drive, optimized for load capacitance < 55 pF. Note: This concerns only stand-alone DDR controller.
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19.7.7 Name: Write Protect Mode Register MATRIX_WPMR Address: 0xFFFFEBE4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – For more details on MATRIX_WPMR, refer to Section 19.6 “Write Protect Registers” on page 135. • WPEN: Write Protect ENable 0 = Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
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19.7.8 Name: Write Protect Status Register MATRIX_WPSR Address: 0xFFFFEBE8 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – For more details on MATRIX_WPSR, refer to Section 19.6 “Write Protect Registers” on page 135. • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR.
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20. External Memories The product embeds two DDRSDR controllers: DDRSDRC0 and DDRSDRC1. Figure 20-1. DDRSDR Controllers DDRSDRC0 Port 3 Port 2 Port 1 DDR2 or LP-DDR Device Port 0 EBI Bus Matrix DDRSDRC1 DDR2 or LP-DDR or SDR or LP-SDR Device Compact Flash Controller Compact Flash Device NAND Flash Controller NAND Flash Device Static Memory Controller Static Memory Device • DDRSDRC0 is a multi-port DDRSDR controller, standalone. It supports only DDR2 and LP-DDR devices.
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20.1 DDRSDRC0 Multi-port DDRSDR Controller 20.1.1 Description The DDR2 Controller is dedicated to 4-port DDR2/LPDDR support. Data transfers are performed through a 16-bit data bus on one chip select. The DDR2 Controller operates with 1.8V Power Supply (VDDIOM0). 20.1.2 Embedded Characteristics 20.1.2.1 DDR2/LPDDR Controller Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes Transaction Latency. • Supports AHB Transfers: – Word, Half Word, Byte Access.
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20.1.3 DDR2 Controller Block Diagram Figure 20-2. Organization of the DDR2 DDR2 DDR_A0-DDR_A13 DDR_D0-DDR_D15 DDR_CS Bus Matrix DDR_CKE DDR_RAS, DDR_CAS DDR2 LPDDR Controller AHB DDR_CLK,#DDR_CLK DDR_DQS[0..1] DDR_DQM[0..
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20.1.4 I/O Lines Description Table 20-1. DDR2 I/O Lines Description Name Function Type Active Level DDR2/LPDDR Controller DDR_D0 - DDR_D15 Data Bus I/O DDR_A0 - DDR_A13 Address Bus Output DDR_DQM0 - DDR_DQM1 Data Mask Output DDR_DQS0 - DDR_DQS1 Data Strobe Output DDR_VREF Reference Voltage for DDR2 operations, typically 0.
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20.1.6.1 2x8-bit DDR2 Hardware Configuration DDR_D[0..15] DDR_A[0..
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20.2 External Bus Interface (EBI) 20.2.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, DDR, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, DDR2 and SDRAM.
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– Programmable Data Float Time • Slow Clock mode supported 20.2.2.
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20.2.3 EBI Block Diagram Figure 20-3.
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20.2.4 I/O Lines Description Table 20-2.
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20.2.5 Application Example 20.2.5.1 Hardware Interface Table 20-4 on page 160 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 20-4.
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Table 20-5.
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Table 20-5. EBI Pins and External Device Connections (Continued) Pins of the Interfaced Device Signals: EBI_ DDR2/LPDDR SDRAM Controller CompactFlash CompactFlash True IDE Mode NAND Flash DDRC SDRAMC NWAIT(5) – – WAIT WAIT (2) Pxx – – CD1 or CD2 CD1 or CD2 – Pxx(2) – – – – CE(3) – – – – RDY Pxx(2) Notes: SMC – 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot. 2.
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20.2.6 Product Dependencies 20.2.6.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller. 20.2.
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User Interface in the Bus Matrix Section.) Access to an external CompactFlash device is then made by accessing the address space reserved to NCS4 and/or NCS5 (i.e., between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled.
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The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller section. Table 20-7.
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Figure 20-6. CompactFlash Read/Write Control Signals External Bus Interface SMC CompactFlash Logic A23 1 1 0 1 0 0 CFOE CFWE 1 1 A22 NRD_NOE NWR0_NWE 0 1 1 Table 20-8.
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Table 20-10. Shared CompactFlash Interface Multiplexing Pins Access to CompactFlash Device Access to Other EBI Devices CompactFlash Signals EBI Signals NWR1/NBS1/CFIOR CFIOR NWR1/NBS1 NWR3/NBS3/CFIOW CFIOW NWR3/NBS3 A25/CFRNW CFRNW A25 Application Example Figure 20-7 on page 167 illustrates an example of a CompactFlash application.
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the NAND Flash logic. For details on this register, refer to the Bus Matrix Section. Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF). The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space.
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20.2.8.1 2x8-bit DDR2 on EBI Hardware Configuration EBI_SDA10 EBI_SDA10 Software Configuration • Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Register located in the bus matrix memory space. • Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency. The DDR2 initialization sequence is described in the sub-section “DDR2 Device Initialization” of the DDRSDRC section.
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20.2.8.2 16-bit LPDDR on EBI Hardware Configuration Software Configuration The following configuration has to be performed: • Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip Select Register located in the bus matrix memory space. • Initialize the DDR2 Controller depending on the LP-DDR device and system bus frequency. The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initialization” in “DDR/SDR SDRAM Controller (DDRSDRC)”.
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20.2.8.3 16-bit SDRAM Hardware Configuration Software Configuration The following configuration has to be performed: • Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits.
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20.2.8.4 2x16-bit SDRAM Hardware Configuration 2 3 4 5 A[1..14] D[0..31] SDRAM MN1 VDDIOM A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 23 24 25 26 29 30 31 32 33 34 22 35 BA0 BA1 20 21 A14 36 40 CKE 37 CLK 38 DQM0 DQM1 15 39 CAS RAS 17 18 WE 16 19 R1 470K MN2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.
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20.2.8.5 8-bit NAND Flash Hardware Configuration D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
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20.2.8.6 16-bit NAND Flash Hardware Configuration D[0..15] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C 10K MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.
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20.2.8.7 NOR Flash on NCS0 Hardware Configuration D[0..15] A[1..
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20.2.8.8 CompactFlash Hardware Configuration MEMORY & I/O MODE D[0..
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• The address line A23 is to select I/O (A23=1) or Memory mode (A23=0) and the address line A22 for REG function. • A22, A23, CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. • Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively.
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20.2.8.9 CompactFlash True IDE Hardware Configuration TRUE IDE MODE D[0..
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• The address line A21 is to select Alternate True IDE (A21=1) or True IDE (A21=0) modes. • A21, CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. • Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively.
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SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 180
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21. Static Memory Controller (SMC) 21.1 Description The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
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21.4 21.4.1 Application Example Hardware Interface Figure 21-1.
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21.6 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 21-2).
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Figure 21-3. Memory Connection for an 8-bit Data Bus D[7:0] D[7:0] A[18:2] A[18:2] SMC A0 A0 A1 A1 NWE Write Enable NRD Output Enable NCS[2] Figure 21-4. Memory Enable Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC A[0] NBS0 Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Memory Enable Figure 21-5.
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21.7.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. • For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
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21.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 21-3 shows signal multiplexing depending on the data bus width and the byte access type. For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused.
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21.8 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 21.8.
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1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. 21.8.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change.
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21.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 21.8.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first.
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Figure 21-11.
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21.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 21-12. The write cycle starts with the address setting on the memory address bus. 21.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3.
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= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE 21.8.3.
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Figure 21-14. WRITE_MODE = 1. The write operation is controlled by NWE MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 21.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 21-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal.
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• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE The SMC_CYCLE register groups the definition of all cycle parameters: • NRD_CYCLE, NWE_CYCLE Table 21-4 shows how the timing parameters are coded and their permitted range. Table 21-4.
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Figure 21-16 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2. Figure 21-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWE NCS0 NCS2 NRD_CYCLE NWE_CYCLE D[31:0] Read to Write Chip Select Wait State Wait State 21.9.
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Figure 21-17. Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NRD no hold no setup D[31:0] write cycle Early Read wait state read cycle Figure 21-18.
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Figure 21-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 internal write controlling signal external write controlling signal (NWE) no hold read setup = 1 NRD D[31:0] write cycle (WRITE_MODE = 1) 21.9.3 Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface.
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21.9.3.2 Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see “Slow Clock Mode” on page 209). 21.9.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document.
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21.10 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: • before starting a read access to a different external memory • before starting a write access to the same device or to a different external one. The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select.
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Figure 21-21. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS tpacc D[31:0] TDF = 3 clock cycles NCS controlled read operation 21.10.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
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Figure 21-22. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK A[25:2] NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[31:0] read access on NCS0 (NRD controlled) 21.10.3 Read to Write Wait State write access on NCS0 (NWE controlled) TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins.
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Figure 21-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[31:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 21-24.
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Figure 21-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[31:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 21.11 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
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21.11.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 21-26.
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Figure 21-27.
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21.11.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 21-28 and Figure 21-29. After deassertion, the access is completed: the hold step of the access is performed.
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Figure 21-29.
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21.11.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
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21.12 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
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21.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 21-32 on page 210. The external device may not be fast enough to support such timings. Figure 21-33 illustrates the recommended procedure to properly switch from one mode to the other. Figure 21-32.
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Figure 21-33.
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21.13 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
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In page mode, the programming of the read timings is described in Table 21-7: Table 21-7. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
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Figure 21-35.
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21.14 Programmable IO Delays The external bus interface consists of a data bus, an address bus and control signals. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, SMC_DELAY1-8. The additional programmable delays for each IO range from 0 to 4 ns (Worst Case PVT).
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21.15 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 21-8. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 21-8, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 21-8.
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21.15.1 Name: SMC Setup Register SMC_SETUP[0..
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21.15.2 Name: SMC Pulse Register SMC_PULSE[0..
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21.15.3 Name: SMC Cycle Register SMC_CYCLE[0..5] Addresses: 0xFFFFE808 [0], 0xFFFFE818 [1], 0xFFFFE828 [2], 0xFFFFE838 [3], 0xFFFFE848 [4], 0xFFFFE858 [5] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 NRD_CYCLE 19 18 17 16 11 – 10 – 9 – 8 NWE_CYCLE 3 2 1 0 NRD_CYCLE 15 – 14 – 13 – 12 – 7 6 5 4 NWE_CYCLE • NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle.
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21.15.4 Name: SMC MODE Register SMC_MODE[0..5] Addresses: 0xFFFFE80C [0], 0xFFFFE81C [1], 0xFFFFE82C [2], 0xFFFFE83C [3], 0xFFFFE84C [4], 0xFFFFE85C [5] Access: Read-write 31 – 30 – 29 23 – 22 – 21 – 15 – 14 – 13 7 – 6 – 5 28 27 – 26 – 20 TDF_MODE 19 18 12 11 – 4 3 – PS DBW EXNW_MODE 25 – 24 PMEN 17 16 10 – 9 – 8 BAT 2 – 1 WRITE_MODE 0 READ_MODE TDF_CYCLES • READ_MODE: 1: The read operation is controlled by the NRD signal.
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• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. • BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
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21.15.5 Name: SMC DELAY I/O Register SMC_DELAY 1-8 Addresses: 0xFFFFE8C0 [1], 0xFFFFE8C4 [2], 0xFFFFE8C8 [3], 0xFFFFE8CC [4], 0xFFFFE8D0 [5], 0xFFFFE8D4 [6], 0xFFFFE8D8 [7], 0xFFFFE8DC [8] Access: Read-write Reset Value: See Table 21-8 31 30 29 28 27 26 Delay8 23 22 21 20 19 18 Delay6 15 14 13 6 24 17 16 9 8 1 0 Delay5 12 11 10 Delay4 7 25 Delay7 Delay3 5 Delay2 4 3 2 Delay1 • Delay x: Gives the number of elements in the delay line.
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22. DDR/SDR SDRAM Controller (DDRSDRC) 22.1 Description The DDR SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol. The DDRSDRC extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDR-SDRAM device and external 16-bit DDR-SDRAM device.
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22.
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22.3 DDRSDRC Module Diagram Figure 22-1.
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22.4 Initialization Sequence The addresses given are for example purposes only. The real address depends on implementation in the product. 22.4.1 SDR-SDRAM Initialization The initialization sequence is generated by software. The SDR-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 22.8.8 on page 263). 2. Program the features of the SDR-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.
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22.4.2 Low-power DDR1-SDRAM Initialization The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 22.8.8 on page 263). 2. Program the features of the low-power DDR1-SDRAM device into the Configuration Register: asynchronous timing (trc, tras, etc.), number of columns, rows, cas latency. See Section 22.8.3 on page 254, Section 22.8.
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22.4.3 DDR2-SDRAM Initialization The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 22.8.8 on page 263). 2. Program the features of DDR2-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows, cas latency and output drive strength) (see Section 22.8.3 on page 254, Section 22.8.
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13. Program DLL field into the Configuration Register (see Section 22.8.3 on page 254) to low (Disable DLL reset). 14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices, in particular CAS latency, burst length and to disable DLL reset. The application must set Mode to 3 in the Mode Register (see Section 22.8.1 on page 252) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1:0] are set to 0.
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22.5 Functional Description 22.5.1 SDRAM Controller Write Cycle The DDRSDRC allows burst access or single access in normal mode (mode = 000). Whatever the access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance. The SDRAM device is programmed with a burst length equal to 8. This determines the length of a sequential data input by the write command that is set to 8. The latency from write command to data input is fixed to 1 in the case of DDR-SDRAM devices.
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Figure 22-2. Single Write Access, Row Closed, Low-power DDR1-SDRAM Device SDCLK Row a A[12:0] COMMAND BA[1:0] PRCHG NOP NOP col a ACT NOP WRITE NOP 00 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da Trp = 2 3 Db Trcd = 2 Figure 22-3.
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Figure 22-4. Single Write Access, Row Closed, SDR-SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] Row a NOP PRCHG NOP ACT Col a NOP WRITE BST NOP 00 3 DM[1:0] 0 D[31:0] 3 DaDb Trp = 2 Trcd = 2 Figure 22-5.
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Figure 22-6. Burst Write Access, Row Closed, DDR2-SDRAM Device SDCLK A[12:0] Row a COMMAND BA[1:0] NOP PRCHG NOP col a ACT NOP WRITE NOP 0 DQS[1:0] DM[1:0] 3 0 D [15:0] Da Db Dc Dd 3 De Df Dg Dh Trcd = 2 Trp = 2 Figure 22-7.
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Figure 22-8. Write Command Followed By a Read Command without Burst Write Interrupt, Low-power DDR1-SDRAM Device SDCLK A[12:0] col a COMMAND NOP BA[1:0] col a WRITE NOP READ BST NOP 0 DQS[1:0] DM[1:0] 3 0 D[15:0] 3 Da Db Dc Dd De Df Dg Dh Da Db Twrd = BL/2 +2 = 8/2 +2 = 6 Twr = 1 In the case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle prior to the read command to avoid writing invalid data.
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Figure 22-10. SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] col a Row a NOP PRCHG NOP ACT NOP WRITE NOP READ NOP 0 DQS[1:0] DM[1:0] D[15:0] 3 0 Da 3 Da Db Db Data masked twtr 22.5.2 SDRAM Controller Read Cycle The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance of the DDRSDRC.
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For a definition of timing parameters, refer to Section 22.8.3 “DDRSDRC Configuration Register” on page 254. Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given read command. When the read command is issued, 8 columns are selected. All accesses for that burst take place within these eight columns, meaning that the burst wraps within these 8 columns if the boundary is reached.
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Figure 22-12. Single Read Access, Row Close, Latency = 3, DDR2-SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] NOP PRCHG NOP Row a Col a ACT NOP READ 0 DQS[1] DQS[0] DM[1:0] 3 D[15:0] Da Trp Db Latency = 2 Trcd Figure 22-13.
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Figure 22-14. Burst Read Access, Latency = 2, Low-power DDR1-SDRAM Devices SDCLK Col a A[12:0] COMMAND BA[1:0] NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Dc Dd De Db Dc Df Dg Dh Latency = 2 Figure 22-15.
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Figure 22-16. Burst Read Access, Latency = 2, SDR-SDRAM Devices SDCLK A[12:0] COMMAND BA[1:0] col a NOP READ NOP BST NOP 0 DQS[1:0] DM[3:0] F D[31:0] DaDb DcDd DeDf Dg Dh Latency = 2 22.5.3 22.5.4 Refresh (Auto-refresh Command) An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The DDRSDRC generates these autorefresh commands periodically.
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parameters and Drive Strength (DS). These parameters are set during the initialization phase.
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Figure 22-18. Self Refresh Mode Entry, Timeout = 1 or 2 SDCLK A[12:0] COMMAND NOP READ BST NOP PRCHG NOP ARFSH NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db 64 or 128 wait states Trp Enter Self refresh Mode Figure 22-19.
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Figure 22-20. Self Refresh and Automatic Update SDCLK Pasr-Tcr-Ds A[12:0] COMMAND NOP PRCHG NOP MRS NOP NOP ARFSH CKE BA[1:0] 0 2 Enter Self Refresh Mode Tmrd Trp Update Extended Mode register Figure 22-21. Automatic Update During AUTO-REFRESH Command and SDRAM Access SDCLK A[12:0] COMMAND Pasr-Tcr-Ds NOP PRCHALL NOP ARFSH NOP MRS NOP ACT CKE BA[1:0] 0 0 2 Trp Trfc Tmrd Update Extended mode register 22.5.4.
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The exit procedure is faster than in self refresh mode. See Figure 22-22 on page 243. The DDRSDRC returns to power-down mode as soon as the SDRAM device is not selected. It is possible to define when power-down mode is enabled by setting the register LPR, timeout command bit.
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Figure 22-23. Deep Power-down Mode Entry SDCLK A[12:0] COMMAND NOP READ BST NOP PRCHG NOP DEEPOWER NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] D[15:0] 3 Da Db Trp Enter Deep Power-down Mode 22.5.4.4 Reset Mode The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-power command bits (LPCB) to 11 and the clock frozen command bit (CLK_FR) to 1. When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen.
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22.5.5 Multi-port Functionality The SDRAM protocol imposes a check of timings prior to performing a read or a write access, thus decreasing the performance of systems. An access to SDRAM is performed if banks and rows are open (or active). To activate a row in a particular bank, it has to de-active the last open row and open the new row. Two SDRAM commands must be performed to open a bank: Precharge and Active command with respect to Trp timing.
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1. Idle cycles: When no master is connected to the SDRAM device. 2. Single cycles: When a slave is currently doing a single access. 3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For bursts of defined length, predicted end of burst matches the size of the transfer. For bursts of undefined length, predicted end of burst is generated at the end of each four beat boundary inside the INCR transfer. 4.
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22.5.6 Write Protected Registers To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be writeprotected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
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22.6 Software Interface/SDRAM Organization, Address Mapping The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps different memory types depending on the values set in the DDRSDRC Configuration Register. See Section 22.8.3 “DDRSDRC Configuration Register” on page 254. The following figures illustrate the relation between CPU addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths.
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Table 22-4. Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 Bk[1:0] 16 15 14 13 12 11 10 9 8 7 6 Row[13:0] Bk[1:0] 5 4 3 2 1 M0 Column[9:0] Row[13:0] 0 M0 Column[8:0] Row[13:0] Bk[1:0] Note: 17 M0 Column[10:0] 1. SDR-SDRAM devices with eight columns in 16-bit mode are not supported. 22.6.2 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width Table 22-5.
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22.7 Programmable IO Delays The external bus interface consists of a data bus, an address bus and control signals. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, DDRSDRC_DELAY1-8.
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22.8 DDR SDR SDRAM Controller (DDRSDRC) User Interface The User Interface is connected to the APB bus. The DDRSDRC is programmed using the registers listed in Table 22-8 Table 22-8.
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22.8.1 Name: DDRSDRC Mode Register DDRSDRC_MR Address: 0xFFFFE600 (0), 0xFFFFE400 (1) Access: Read-write Reset: See Table 22-8 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 MODE 0 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 267.
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22.8.2 Name: DDRSDRC Refresh Timer Register DDRSDRC_RTR Address: 0xFFFFE604 (0), 0xFFFFE404 (1) Access: Read-write Reset: See Table 22-8 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 COUNT 3 2 COUNT This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 267.
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22.8.3 Name: DDRSDRC Configuration Register DDRSDRC_CR Address: 0xFFFFE608 (0), 0xFFFFE408 (1) Access: Read-write Reset: See Table 22-8 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 ACTBST 17 – 16 EBISHARE 15 – 14 13 OCD 12 11 – 10 – 9 DIS_DLL 8 DIC/DS 7 DLL 6 5 CAS 4 3 2 1 NR 0 NC This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 267.
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• CAS: CAS Latency The reset value is 2 cycles. CAS DDR2 CAS Latency SDR CAS Latency 000 Reserved Reserved 001 Reserved Reserved 010 Reserved 2 011 3 3 100 Reserved Reserved 101 Reserved Reserved 110 Reserved Reserved 111 Reserved Reserved • DLL: Reset DLL Reset value is 0. This field defines the value of Reset DLL. 0 = Disable DLL reset. 1 = Enable DLL reset. This value is used during the power-up sequence. Note: This field is found only in DDR2-SDRAM devices.
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Note: This field is found only in DDR2-SDRAM devices. OCD 000 OCD calibration mode exit, maintain setting 111 OCD calibration default • EBISHARE: External Bus Interface is Shared The DDR controller embedded in the EBI is used at the same time as another memory controller (SMC,..) Reset value is 0. 0 = Only the DDR controller function is used. 1 = The DDR controller shares the EBI with another memory controller (SMC, NAND,..) • ACTBST: ACTIVE Bank X to Burst Stop Read Access Bank Y Reset value is 0.
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22.8.4 Name: DDRSDRC Timing Parameter 0 Register DDRSDRC_TPR0 Address: 0xFFFFE60C (0), 0xFFFFE40C (1) Access: Read-write Reset: See Table 22-8 31 30 29 28 27 REDUCE_WRRD 26 21 20 19 18 TMRD 23 22 TRRD 15 14 13 6 24 17 16 9 8 1 0 TRP 12 11 10 TRC 7 25 TWTR TWR 5 TRCD 4 3 2 TRAS This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 267. • TRAS: Active to Precharge Delay Reset Value is 5 cycles.
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• TWTR: Internal Write to Read Delay Reset value is 0. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices. This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 7.
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22.8.5 Name: DDRSDRC Timing Parameter 1 Register DDRSDRC_TPR1 Address: 0xFFFFE610 (0), 0xFFFFE410 (1) Access: Read-write Reset: See Table 22-8 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 TXP 19 18 17 16 11 10 9 8 3 2 TRFC 1 0 TXSRD 15 14 13 12 TXSNR 7 – 6 – 5 – 4 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 267. • TRFC: Row Cycle Delay Reset Value is 8 cycles.
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22.8.6 Name: DDRSDRC Timing Parameter 2 Register DDRSDRC_TPR2 Address: 0xFFFFE614 (0), 0xFFFFE414 (1) Access: Read-write Reset: See Table 22-8 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 TRTP 12 11 10 9 8 5 4 1 0 7 6 TRPA TXARDS 3 2 TXARD This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 267.
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22.8.7 Name: DDRSDRC Low-power Register DDRSDRC_LPR Address: 0xFFFFE61C (0), 0xFFFFE41C (1) Access: Read-write Reset: See Table 22-8 31 – 30 – 29 – 23 – 22 – 21 15 – 14 – 13 7 – 6 5 PASR 28 – 27 – 26 – 25 – 24 – 20 19 – 18 – 17 – 16 APDE 12 11 10 9 UPD_MR TIMEOUT DS 4 3 8 TCR 2 CLK_FR 1 0 LPCB • LPCB: Low-power Command Bit Reset value is “00”. 00 = Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
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This field is unique to Low-power SDRAM. It is used to program the refresh interval during self refresh mode, depending on the case temperature of the low-power SDRAM. The values of this field are dependent on Low-power SDRAM devices. After the initialization sequence, as soon as TCR field is modified, Extended Mode Register is accessed automatically and TCR bits are updated.
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22.8.8 Name: DDRSDRC Memory Device Register DDRSDRC_MD Address: 0xFFFFE620 (0), 0xFFFFE420 (1) Access: Read-write Reset: See Table 22-8 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 DBW 3 – 2 1 MD 0 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 267. • MD: Memory Device Indicates the type of memory used.
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22.8.9 DDRSDRC DLL Register Name: DDRSDRC_DLL Address: 0xFFFFE624 (0), 0xFFFFE424 (1) Access: Read-only Reset: See Table 22-8 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 MDOVF 1 MDDEC 0 MDINC MDVAL 7 – 6 – 5 – 4 – The DLL logic is internally used by the controller in order to delay DQS inputs. This is necessary to center the strobe time and the data valid window.
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22.8.10 Name: DDRSDRC High Speed Register DDRSDRC_HS Address: 0xFFFFE62C (0), 0xFFFFE42C (1) Access: Read-write Reset: See Table 22-8 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 1 0 – – – – – 2 DIS_ANTICIP_RE AD – – This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 267.
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22.8.11 Name: DDRSDRC DELAY I/O Register DDRSDRC_DELAYx [x=1..4] Address: 0xFFFFE640 (0), 0xFFFFE440 (1) Access: Read-write Reset: See Table 22-8 31 30 29 28 27 26 DELAY8 23 22 21 20 19 18 DELAY6 15 14 13 6 24 17 16 9 8 1 0 DELAY5 12 11 10 DELAY4 7 25 DELAY7 DELAY3 5 DELAY2 4 3 2 DELAY1 • DELAYx: Delay1..Delay8 Gives the number of elements in the delay line.
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22.8.12 Name: DDRSDRC Write Protect Mode Register DDRSDRC_WPMR Address: 0xFFFFE6E4 (0), 0xFFFFE4E4 (1) Access: Read-write Reset: See Table 22-8 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 — 6 — 5 — 4 — • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
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22.8.13 Name: DDRSDRC Write Protect Status Register DDRSDRC_WPSR Address: 0xFFFFE6E8 (0), 0xFFFFE4E8 (1) Access: Read-only Reset: See Table 22-8 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DDRSDRC_WPSR register.
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23. Error Corrected Code Controller (ECC) 23.1 Description NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur which can be detected/corrected by ECC code. The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data.
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Page size is configured setting the PAGESIZE field in the ECC Mode Register (ECC_MR). Type of correction is configured setting the TYPeCORRECT field in the ECC Mode Register (ECC_MR). ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND Flash or the SmartMedia is detected. Read and write access must start at a page boundary. ECC results are available as soon as the counter reaches the end of the main area.
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Figure 23-2.
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(Page size -3 )th word (Page size -2 )th word (Page size -1 )th word Page size th word 1st word 2nd word 3rd word 4th word (+) Figure 23-3. Parity Generation for 512/1024/2048/4096 16-bit Words To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
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Page size = 2n for i =0 to n begin for (j = 0 to page_size_word) begin if(j[i] ==1) P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2n+3] else P[2i+3]’=bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 273
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23.4 Error Corrected Code Controller (ECC) User Interface Table 23-1.
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23.4.1 Name: ECC Control Register ECC_CR Access: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 SRST 24 – 16 – 8 – 0 RST • RST: RESET Parity Provides reset to current ECC by software. 1: Reset ECC Parity registers 0: No effect • SRST: Soft Reset Provides soft reset to ECC block 1: Resets all registers. 0: No effect.
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23.4.2 Name: Access: 31 – 23 – 15 – 7 – ECC Mode Register ECC_MR Read-write 30 – 22 – 14 – 6 – 29 28 – – 21 20 – – 13 12 – – 5 4 TYPECORRECT 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 24 – 16 – 8 – 0 PAGESIZE • PAGESIZE: Page Size This field defines the page size of the NAND Flash device. Page Size Description 00 528 words 01 1056 words 10 2112 words 11 4224 words A word has a value of 8 bits or 16 bits, depending on the NAND Flash or SmartMedia memory organization.
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23.4.3 Name: Access: 31 – 23 – 15 – 7 – ECC Status Register 1 ECC_SR1 Read-only 30 MULERR7 22 MULERR5 14 MULERR3 6 MULERR1 29 ECCERR7 21 ECCERR5 13 ECCERR3 5 ECCERR1 28 RECERR7 20 RECERR5 12 RECERR3 4 RECERR1 27 – 19 – 11 – 3 – 26 MULERR6 18 MULERR4 10 MULERR2 2 MULERR0 25 ECCERR6 17 ECCERR4 9 ECCERR2 1 ECCERR0 24 RECERR6 16 RECERR4 8 RECERR2 0 RECERR0 • RECERR0: Recoverable Error 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected.
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• RECERR2: Recoverable Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected. • ECCERR2: ECC Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes.
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• ECCERR4: ECC Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 4 register, the error occurred at the location which contains a 1 in the least significant 24 bits. • MULERR4: Multiple Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected.
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• MULERR6: Multiple Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. • RECERR7: Recoverable Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.
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23.4.4 Name: Access: 31 – 23 – 15 – 7 – ECC Status Register 2 ECC_SR2 Read-only 30 MULERR15 22 MULERR13 14 MULERR11 6 MULERR9 29 ECCERR15 21 ECCERR13 13 ECCERR11 5 ECCERR9 28 RECERR15 20 RECERR13 12 RECERR11 4 RECERR9 27 – 19 – 11 – 3 – 26 MULERR14 18 MULERR12 10 MULERR10 2 MULERR8 25 ECCERR14 17 ECCERR12 9 ECCERR10 1 ECCERR8 24 RECERR14 16 RECERR12 8 RECERR10 0 RECERR8 • RECERR8: Recoverable Error in the page between the 2048th and the 2303rd bytes Fixed to 0 if TYPECORREC = 0.
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1 = Multiple Errors Detected. • RECERR10: Recoverable Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected. • ECCERR10: ECC Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes.
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0 = No Errors Detected 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 12 register, the error occurred at the location which contains a 1 in the least significant 24 bits. • MULERR12: Multiple Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. • RECERR13: Recoverable Error in the page between the 3328th and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected.
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• RECERR15: Recoverable Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected • ECCERR15: ECC Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes.
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23.5 Registers for 1 ECC for a page of 512/1024/2048/4096 bytes 23.5.1 Name: ECC Parity Register 0 ECC_PR0 Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 3 2 25 – 17 – 9 24 – 16 – 8 1 0 WORDADDR WORDADDR BITADDR Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.5.
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23.6 Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 23.6.1 Name: 8-bit word ECC Parity Register 0 ECC_PR0 Access: Read-only 31 – 23 30 – 22 29 – 21 15 14 13 7 6 28 – 20 NPARITY0 12 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 4 3 2 1 BITADDR0 0 NPARITY0 5 WORDADDR0 WORDADD0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.6.2 Name: ECC Parity Register 1 ECC_PR1 Access: Read-only 31 – 23 30 – 22 15 14 29 – 21 13 28 – 20 NPARITY1 12 27 – 19 26 – 18 11 10 NPARITY1 7 6 5 WORDADDR1 25 – 17 24 – 16 9 8 1 BITADDR1 0 WORDADD1 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.6.3 Name: ECC Parity Register 2 ECC_PR2 Access: Read-only 31 – 23 30 – 22 15 14 29 – 21 13 28 – 20 NPARITY2 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR2 2 1 BITADDR2 NPARITY2 7 6 5 WORDADDR2 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.6.4 Name: ECC Parity Register 3 ECC_PR3 Access: Read-only 31 – 23 30 – 22 15 14 29 – 21 13 28 – 20 NPARITY3 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR3 2 1 BITADDR3 NPARITY3 7 6 5 WORDADDR3 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.6.5 Name: ECC Parity Register 4 ECC_PR4 Access: Read-only 31 – 23 30 – 22 15 14 29 – 21 13 28 – 20 NPARITY4 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR4 2 1 BITADDR4 NPARITY4 7 6 5 WORDADDR4 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.6.6 Name: ECC Parity Register 5 ECC_PR5 Access: Read-only 31 – 23 30 – 22 15 14 29 – 21 13 28 – 20 NPARITY5 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR5 2 1 BITADDR5 NPARITY5 7 6 5 WORDADDR5 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.6.7 Name: ECC Parity Register 6 ECC_PR6 Access: Read-only 31 – 23 30 – 22 15 14 29 – 21 13 28 – 20 NPARITY6 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR6 2 1 BITADDR6 NPARITY6 7 6 5 WORDADDR6 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.6.8 Name: ECC Parity Register 7 ECC_PR7 Access: Read-only 31 – 23 30 – 22 15 14 29 – 21 13 28 – 20 NPARITY7 12 27 – 19 26 – 18 11 4 3 10 9 WORDADDR7 2 1 BITADDR7 NPARITY7 7 6 5 WORDADDR7 25 – 17 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7 Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 23.7.1 Name: 8-bit word ECC Parity Register 0 ECC_PR0 Access: Read-only 31 – 23 0 15 30 – 22 29 – 21 28 – 20 14 13 12 7 6 NPARITY0 5 WORDADDR0 4 27 – 19 NPARITY0 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR0 1 BITADDR0 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.
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23.7.3 Name: ECC Parity Register 2 ECC_PR2 Access: 31 – 23 0 15 Read-only 30 – 22 14 29 – 21 28 – 20 13 12 NPARITY2 7 6 5 WORDADDR2 4 27 – 19 NPARITY2 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADD2 1 BITADDR2 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.4 Name: ECC Parity Register 3 ECC_PR3 Access: 31 – 23 0 15 Read-only 30 – 22 14 29 – 21 28 – 20 13 12 NPARITY3 7 6 5 WORDADDR3 4 27 – 19 NPARITY3 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR3 1 BITADDR3 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.
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23.7.6 Name: ECC Parity Register 5 ECC_PR5 Access: 31 – 23 0 15 Read-only 30 – 22 14 29 – 21 28 – 20 13 12 NPARITY5 7 6 5 WORDADDR5 4 27 – 19 NPARITY5 11 0 3 26 – 18 10 2 25 – 17 9 WORDADDR5 1 BITADDR5 24 – 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.7 Name: ECC Parity Register 6 ECC_PR6 Access: 31 – 23 0 15 Read-only 30 – 22 14 29 – 21 28 – 20 13 12 NPARITY6 7 6 5 WORDADDR6 4 27 – 19 NPARITY6 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR6 1 BITADDR6 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.8 Name: ECC Parity Register 7 ECC_PR7 Access: 31 – 23 0 15 Read-only 30 – 22 14 29 – 21 28 – 20 13 12 NPARITY7 7 6 5 WORDADDR7 4 27 – 19 NPARITY7 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR7 1 BITADDR7 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.9 Name: ECC Parity Register 8 ECC_PR8 Access: 31 – 23 0 15 Read-only 30 – 22 14 29 – 21 28 – 20 13 12 NPARITY8 7 6 5 WORDADDR8 4 27 – 19 NPARITY8 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR8 1 BITADDR8 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.
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23.7.11 Name: ECC Parity Register 10 ECC_PR10 Access: 31 – 23 0 15 7 Read-only 30 – 22 29 – 21 14 13 NPARITY10 6 5 WORDADDR10 28 – 20 12 4 27 – 19 NPARITY10 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR10 1 BITADDR10 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.12 Name: ECC Parity Register 11 ECC_PR11 Access: 31 – 23 0 15 7 Read-only 30 – 22 29 – 21 14 13 NPARITY11 6 5 WORDADDR11 28 – 20 12 4 27 – 19 NPARITY11 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR11 1 BITADDR11 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.13 Name: ECC Parity Register 12 ECC_PR12 Access: 31 – 23 0 15 7 Read-only 30 – 22 29 – 21 14 13 NPARITY12 6 5 WORDADDR12 28 – 20 12 4 27 – 19 NPARITY12 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR12 1 BITADDR12 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.14 Name: ECC Parity Register 13 ECC_PR13 Access: 31 – 23 0 15 7 Read-only 30 – 22 29 – 21 14 13 NPARITY13 6 5 WORDADDR13 28 – 20 12 4 27 – 19 NPARITY13 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR13 1 BITADDR13 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.15 Name: ECC Parity Register 14 ECC_PR14 Access: 31 – 23 0 15 7 Read-only 30 – 22 29 – 21 14 13 NPARITY14 6 5 WORDADDR14 28 – 20 12 4 27 – 19 NPARITY14 11 0 3 26 – 18 25 – 17 24 – 16 10 9 WORDADDR14 1 BITADDR14 8 2 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
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23.7.
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24. Peripheral DMA Controller (PDC) 24.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves.
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Table 24-1. 24.3 Peripheral DMA Controller (Continued) Instance name Channel T/R SPI0 Receive SSC1 Receive SSC0 Receive Block Diagram Figure 24-1.
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24.4 Functional Description 24.4.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
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These status flags are described in the Peripheral Status Register. 24.4.4 Data Transfers The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface. When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix.
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24.5 Peripheral DMA Controller (PDC) User Interface Table 24-2.
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24.5.1 Name: Receive Pointer Register PERIPH_RPR Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. 24.5.
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24.5.3 Name: Transmit Pointer Register PERIPH_TPR Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. 24.5.
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24.5.5 Name: Receive Next Pointer Register PERIPH_RNPR Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 24.5.
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24.5.7 Name: Transmit Next Pointer Register PERIPH_TNPR Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 24.5.
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24.5.9 Name: Transfer Control Register PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN • RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables PDC receiver channel requests if RXTDIS is not set.
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24.5.10 Name: Transfer Status Register PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN • RXTEN: Receiver Transfer Enable 0 = PDC Receiver channel requests are disabled. 1 = PDC Receiver channel requests are enabled. • TXTEN: Transmitter Transfer Enable 0 = PDC Transmitter channel requests are disabled.
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SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 322
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25. Clock Generator 25.1 Description The Clock Generator User Interface is embedded within the Power Management Controller Interface and is described in Section 26.11. However, the Clock Generator registers are named CKGR_. 25.
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25.3 Slow Clock Crystal Oscillator The Clock Generator integrates a 32,768 Hz low-power oscillator. The XIN32 and XOUT32 pins must be connected to a 32,768 Hz crystal. Two external capacitors must be wired as shown in Figure 25-2. Figure 25-2. Typical Slow Clock Crystal Oscillator Connection XIN32 XOUT32 GNDOSC 32,768 Hz Crystal 25.4 Slow Clock RC Oscillator The user has to take into account the possible drifts of the RC Oscillator.
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25.5.1 Switch from Internal RC Oscillator to the 32768 Hz Crystal To switch from internal RC oscillator to the 32768 Hz crystal, the programmer must execute the following sequence: • Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator) through the Power management Controller. • Enable the 32768 Hz oscillator by setting the bit OSCEN to 1.
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25.5.
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25.6 Main Oscillator The Main Oscillator is designed for a 12 MHz fundamental crystal. The 12 MHz is an input of the PLLA and the UPLL used to generate the 480 MHz USB High Speed Clock (UPLLCK). Figure 25-4 shows the Main Oscillator block diagram. Figure 25-4. Main Oscillator Block Diagram XIN 12M Main Oscillator Main Clock MAINCK XOUT UPLL PLLA and Divider 25.6.1 UPLLCK PLLA Clock PLLACK Main Oscillator Connections The typical crystal connection is illustrated in Figure 25-5.
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from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor. 25.6.4 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin.
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25.8 UTMI Bias and Phase Lock Loop Programming The multiplier is built-in to 40 to obtain the USB High Speed 480 MHz. UPLLEN MAINCK UPLL UPLLCK PLLCOUNT SLCK UPLL Counter LOCKU Whenever the UPLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UPLL counter. The UPLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0.
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26. Power Management Controller (PMC) 26.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. 26.2 Embedded Characteristics The Power Management Controller provides all the clock signals to the system.
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Figure 26-1. SAM9M10 Power Management Controller Block Diagram PLLACK USBS UHP48M USBDIV+1 USB OHCI UHP12M /4 USB EHCI /1,/2 PCK Processor Clock Controller UPLLCK int Divider MAINCK SLCK Prescaler /1,/2,/4,.../64 X /1 /1.5 /2 SysClk DDR /1 /2 MCK /3 /4 Peripherals Clock Controller ON/OFF Master Clock Controller SLCK MAINCK periph_clk[..] ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] UPLLCK Programmable Clock Controller 26.2.
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26.2.1.3 No UDP HS, UHP FS and DDR2 Mode • Only PLLA is running at 384 MHz, UPLL power consumption is saved • USB Device High Speed and Host EHCI High Speed operations are NOT allowed • Full Speed OHCI input clock is PLLACK, USBDIV is 7 (division by 8) • System Input clock is PLLACK, PCK is 384 MHz • MDIV is ‘11’, MCK is 128 MHz • DDR2 can be used at up to 128 MHz 26.3 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK).
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The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock and entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any enabled fast or normal interrupt, or by reset of the product. Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation.
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In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 26.
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raised if the associated interrupt to LOCKA has been enabled in the PMC_IER register. All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage one of the following parameters, MULA, DIVA is modified, LOCKA bit will go low to indicate that PLLA is not ready yet. When PLLA is locked, LOCKA will be set again. The user is constrained to wait for LOCKA bit to be set before using the PLLA output clock.
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– Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. • If a new value for CSS field corresponds to Main Clock or Slow Clock, – Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. – Program the PRES field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register.
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If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable clock and wait for the PCKRDYx bit to be set. Code Example: write_register(PMC_PCK0,0x00000015) Programmable clock 0 is main clock divided by 32. 6.
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26.10 Clock Switching Details 26.10.1 Master Clock Switching Timings Table 26-1 gives the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 26-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLLA Clock – 4 x SLCK + 2.
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Figure 26-4. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR Figure 26-5.
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Figure 26-6.
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26.11 Power Management Controller (PMC) User Interface Table 26-2.
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26.11.1 Name: PMC System Clock Enable Register PMC_SCER Address: 0xFFFFFC00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 – UHP – – – DDRCK – – • DDRCK: DDR Clock Enable 0 = No effect. 1 = Enables the DDR clock. • UHP: USB Host OHCI Clocks Enable 0 = No effect. 1 = Enables the UHP48M and UHP12M OHCI clocks.
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26.11.2 Name: PMC System Clock Disable Register PMC_SCDR Address: 0xFFFFFC04 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 – UHP – – – DDRCK – PCK • PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode. • DDRCK: DDR Clock Disable 0 = No effect.
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26.11.3 Name: PMC System Clock Status Register PMC_SCSR Address: 0xFFFFFC08 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 – UHP – – – DDRCK – PCK • PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled. • DDRCK: DDR Clock Status 0 = The DDR clock is disabled.
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26.11.4 Name: PMC Peripheral Clock Enable Register PMC_PCER Address: 0xFFFFFC10 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0 = No effect.
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26.11.5 Name: PMC Peripheral Clock Disable Register PMC_PCDR Address: 0xFFFFFC14 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Disable 0 = No effect.
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26.11.
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26.11.7 Name: PMC UTMI Clock Configuration Register CKGR_UCKR Address: 0xFFFFFC1C Access: Read/Write 31 30 29 28 27 – 26 – 25 – 24 BIASEN 21 20 19 – 18 – 17 – 16 UPLLEN BIASCOUNT 23 22 PLLCOUNT 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • UPLLEN: UTMI PLL Enable 0 = The UTMI PLL is disabled. 1 = The UTMI PLL is enabled. When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
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26.11.8 Name: PMC Clock Generator Main Oscillator Register CKGR_MOR Address: 0xFFFFFC20 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 OSCBYPASS 0 MOSCEN OSCOUNT 7 – 6 – 5 – 4 – • MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Oscillator is disabled. 1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0.
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26.11.9 Name: PMC Clock Generator Main Clock Frequency Register CKGR_MCFR Address: 0xFFFFFC24 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled.
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26.11.10 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read/Write 31 – 30 – 29 1 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 10 9 8 2 1 0 MULA 15 14 13 12 11 OUTA 7 PLLACOUNT 6 5 4 3 DIVA Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
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26.11.11 PMC USB Clock Register Name: PMC_USB Address: 0xFFFFFC38 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – USBDIV 7 6 5 4 3 2 1 0 – – – – – – – USBS • USBS: USB OHCI Input clock selection 0 = USB Clock Input is PLLA 1 = USB Clock Input is UPLL • USBDIV: Divider for USB OHCI Clock.
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26.11.12 PMC Master Clock Register Name: PMC_MCKR Address: 0xFFFFFC30 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – PLLADIV2 – – 4 3 2 7 6 5 – – – MDIV 1 PRES 0 CSS • CSS: Master/Processor Clock Source Selection CSS Clock Source Selection 0 0 Slow Clock is selected. 0 1 Main Clock is selected. 1 0 PLLA Output clock is selected.
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• MDIV: Master Clock Division MDIV 0 0 Master Clock is Prescaler Output Clock divided by 1. Warning: SysClk DDR and DDRCK are not available. 0 1 Master Clock is Prescaler Output Clock divided by 2. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. 1 0 Master Clock is Prescaler Output Clock divided by 4. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. 1 Master Clock is Prescaler Output Clock divided by 3. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
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26.11.13 PMC Programmable Clock Register Name: PMC_PCKx Address: 0xFFFFFC40 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SLCKMCK 4 3 2 1 7 6 5 – – – PRES 0 CSS • CSS: Master Clock Selection CSS Clock Source Selection 0 0 Slow Clock or Master Clock may be selected depending on SLCKMCK field. 0 1 Main Clock is selected.
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26.11.
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26.11.
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26.11.16 PMC Status Register Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 – LOCKU – – MCKRDY – LOCKA MOSCS • MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized. • LOCKA: PLLA Lock Status 0 = PLLA is not locked 1 = PLLA is locked.
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26.11.
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26.11.
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27. Serial Peripheral Interface (SPI) 27.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
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27.3 Block Diagram Figure 27-1. Block Diagram PDC APB SPCK MISO PMC MOSI MCK SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt Figure 27-2. Block Diagram AHB Matrix DMA Ch.
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27.4 Application Block Diagram Figure 27-3.
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27.5 Signal Description Table 27-1. Signal Description Type Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input 27.6 Product Dependencies 27.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
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27.6.3 Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).Handling the SPI interrupt requires programming the AIC before configuring the SPI. Table 27-3. Peripheral IDs Instance ID SPI0 14 SPI1 15 27.6.4 Peripheral DMA Controller (PDMA) Direct Memory Access Controller (DMAC) The SPI interface can be used in conjunction with the PDMA DMAC in order to reduce processor overhead.
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Figure 27-4. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 27-5.
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27.7.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
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27.7.3.1 Master Mode Block Diagram Figure 27-6. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
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27.7.3.2 Master Mode Flow Diagram Figure 27-7. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
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Figure 27-8.
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27.7.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
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Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the SPI_TDR register as the following format. [xxxxxxx(7-bit) + LASTXFER(1-bit)(1)+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip select to assert as defined in Section 27.8.
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27.7.3.8 SPI Direct Access Memory Controller (DMAC) In both fixed and variable mode the Direct Memory Access Controller (DMAC) can be used to reduce processor overhead. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the DMAC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed.
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Figure 27-11. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI Slave 0 Slave 1 Slave 14 NSS NSS SPI Master NSS NPCS0 NPCS1 NPCS2 NPCS3 1-of-n Decoder/Demultiplexer 27.7.3.
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27.7.3.12 Peripheral Deselection with DMAC When the Direct Memory Access Controller is used, the chip select line will remain low during the whole transfer since the TDRE flag is managed by the DMAC itself. The reloading of the SPI_TDR by the DMAC is done as soon as TDRE flag is set to one. In this case the use of CSAAT bit might not be needed.
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By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR). 27.7.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master.
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27.8 Serial Peripheral Interface (SPI) User Interface Table 27-5.
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27.8.1 Name: SPI Control Register SPI_CR Addresses: 0xFFFA4000 (0), 0xFFFA8000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI.
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27.8.2 Name: SPI Mode Register SPI_MR Addresses: 0xFFFA4004 (0), 0xFFFA8004 (1) Access: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.
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LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS.
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27.8.3 Name: SPI Receive Data Register SPI_RDR Addresses: 0xFFFA4008 (0), 0xFFFA8008 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
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27.8.4 Name: SPI Transmit Data Register SPI_TDR Addresses: 0xFFFA400C (0), 0xFFFA800C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
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27.8.
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• TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.
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27.8.6 Name: SPI Interrupt Enable Register SPI_IER Addresses: 0xFFFA4014 (0), 0xFFFA8014 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = No effect. 1 = Enables the corresponding interrupt.
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27.8.7 Name: SPI Interrupt Disable Register SPI_IDR Addresses: 0xFFFA4018 (0), 0xFFFA8018 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = No effect. 1 = Disables the corresponding interrupt.
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27.8.8 Name: SPI Interrupt Mask Register SPI_IMR Addresses: 0xFFFA401C (0), 0xFFFA801C (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
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27.8.9 Name: SPI Chip Select Register SPI_CSR0... SPI_CSR3 Addresses: 0xFFFA4030 (0), 0xFFFA8030 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS Note: 3 2 1 0 CSAAT – NCPHA CPOL SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written.
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BITS 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer Reserved Reserved Reserved Reserved Reserved Reserved Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCK SPCK Baudrate = --------------SCBR Programming the SCBR field at 0 is forbidden.
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SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 390
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28. Advanced Interrupt Controller (AIC) 28.1 Description The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and realtime overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
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28.3 Block Diagram Figure 28-1. Block Diagram FIQ AIC ARM Processor IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded nFIQ nIRQ Peripheral Embedded Peripheral APB 28.4 Application Block Diagram Figure 28-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 28.
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28.6 I/O Line Description Table 28-1. I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0 - IRQn Interrupt 0 - Interrupt n Input 28.7 Product Dependencies 28.7.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function.
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28.8 28.8.1 Functional Description Interrupt Source Control 28.8.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode.
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28.8.1.5 Figure 28-4. Internal Interrupt Source Input Stage Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Edge AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR 28.8.1.6 External Interrupt Source Input Stage Figure 28-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg.
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28.8.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. • Occurrence, either at the processor level or at the AIC level. • The execution time of the instruction in progress when the interrupt occurs. • The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations.
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28.8.2.3 Internal Interrupt Edge Triggered Source Figure 28-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active 28.8.2.4 Internal Interrupt Level Sensitive Source Figure 28-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 28.8.3 Normal Interrupt 28.8.3.
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28.8.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted.
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1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR.
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Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled. 28.8.4.3 Fast Interrupt Vectoring The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register).
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28.8.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source.
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28.8.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR.
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enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. 28.8.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode.
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28.9 Advanced Interrupt Controller (AIC) User Interface 28.9.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-KByte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a ± 4-KByte offset. Table 28-3.
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28.9.2 Name: AIC Source Mode Register AIC_SMR0..AIC_SMR31 Address: 0xFFFFF000 Access: Read-write Reset Value: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 4 – 3 – 2 1 PRIOR 0 SRCTYPE • PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest).
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28.9.3 Name: AIC Source Vector Register AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access: Read-write Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. 28.9.
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28.9.5 Name: AIC FIQ Register AIC_FVR Address: 0xFFFFF104 Access: Read-only Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. 28.9.
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28.9.7 Name: AIC Interrupt Pending Register AIC_IPR Address: 0xFFFFF10C Access: Read-only Reset Value: 0x0 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 SYS 0 FIQ • FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt is not pending.
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28.9.9 Name: AIC Core Interrupt Status Register AIC_CISR Address: 0xFFFFF114 Access: Read-only Reset Value: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 NIRQ 0 NFIQ • NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active. 28.9.
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28.9.11 Name: AIC Interrupt Disable Command Register AIC_IDCR Address: 0xFFFFF124 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 SYS 0 FIQ • FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt. 28.9.
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28.9.13 Name: AIC Interrupt Set Command Register AIC_ISCR Address: 0xFFFFF12C Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 SYS 0 FIQ • FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt. 28.9.
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28.9.15 Name: AIC Spurious Interrupt Vector Register AIC_SPU Address: 0xFFFFF134 Access: Read-write Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
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28.9.17 Name: AIC Fast Forcing Enable Register AIC_FFER Address: 0xFFFFF140 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 SYS 0 – • SYS, PID2-PID31: Fast Forcing Enable 0 = No effect.
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28.9.19 Name: AIC Fast Forcing Status Register AIC_FFSR Address: 0xFFFFF148 Access: Read-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 SYS 0 – • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt.
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29. Debug Unit (DBGU) 29.1 Description The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication.
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29.3 Block Diagram Figure 29-1. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive DRXD COMMRX ARM Processor COMMTX DCC Handler Chip ID nTRST ICE Access Handler Interrupt Control dbgu_irq Power-on Reset force_ntrst Table 29-1.
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29.4 Product Dependencies 29.4.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. Table 29-2. I/O Lines Instance Signal I/O Line Peripheral DBGU DRXD PB12 A DBGU DTXD PB13 A 29.4.
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Figure 29-3. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 29.5.2 Receiver 29.5.2.1 Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
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Figure 29-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 29.5.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 29-6.
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29.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 29-9. Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 29.5.
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29.5.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR.
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Figure 29-12. Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter 29.5.6 TXD VDD Disabled Disabled RXD TXD Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
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29.5.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
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29.6 Debug Unit (DBGU) User Interface Table 29-3.
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29.6.1 Name: Debug Unit Control Register DBGU_CR Address: 0xFFFFEE00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
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29.6.
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29.6.
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29.6.
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29.6.
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29.6.6 Name: Debug Unit Status Register DBGU_SR Address: 0xFFFFEE14 Access: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
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1 = The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. • COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive.
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29.6.7 Name: Debug Unit Receiver Holding Register DBGU_RHR Address: 0xFFFFEE18 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set. 29.6.
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29.6.
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29.6.10 Name: Debug Unit Chip ID Register DBGU_CIDR Address: 0xFFFFEE40 Access: Read-only 31 EXT 30 23 22 29 NVPTYP 28 21 20 27 26 19 18 ARCH 15 14 13 6 EPROC 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 3 2 VERSION • VERSION: Version of the Device Values depend upon the version of the device.
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• NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 Size 0 0 0 0 None 0 0 0 1 8K bytes 0 0 1 0 16K bytes 0 0 1 1 32K bytes 0 1 0 0 Reserved 0 1 0 1 64K bytes 0 1 1 0 Reserved 0 1 1 1 128K bytes 1 0 0 0 Reserved 1 0 0 1 256K bytes 1 0 1 0 512K bytes 1 0 1 1 Reserved 1 1 0 0 1024K bytes 1 1 0 1 Reserved 1 1 1 0 2048K bytes 1 1 1 1 Reserved • SRAMSIZ: Internal SRAM Size SRAMSIZ Size 0 0 0 0 Reserved 0 0 0 1 1K byt
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• ARCH: Architecture Identifier ARCH Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x37 0011 0111 CAP7 Series 0x39 0011 1001 CAP9 Series 0x3B 0011 1011 CAP11 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0110 0000 AT91SAM7Axx Series 0x61 0110 0001 AT91SAM7AQxx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 011
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29.6.11 Name: Debug Unit Chip ID Extension Register DBGU_EXID Address: 0xFFFFEE44 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
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29.6.12 Name: Debug Unit Force NTRST Register DBGU_FNR Address: 0xFFFFEE48 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST • FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor’s TAP controller is held low.
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30. Parallel Input/Output Controller (PIO) 30.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
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30.2 Block Diagram Figure 30-1. Block Diagram PIO Controller AIC PMC PIO Interrupt PIO Clock Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 30-2.
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30.3 Product Dependencies 30.3.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
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30.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 30-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 30-3.
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30.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
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ages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 30.4.
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Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 30.4.9 Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted.
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Figure 30-6. Input Change Interrupt Timings MCK Pin Level PIO_ISR Read PIO_ISR 30.4.11 APB Access APB Access Write Protected Registers To prevent any single software error that may corrupt the PIO behavior, the registers listed below can be write-protected by setting the WPEN bit in the PIO Write Protect Mode Register (PIO_WPMR).
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30.4.12 Programmable I/O Delays The PIO interface consists of a series of signals driven by peripherals or directly by sofware. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, PIO_DELAY.
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30.5 I/O Lines Programming Example The programing example as shown in Table 30-1 below is used to define the following configuration.
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30.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 30-2.
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Table 30-2.
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30.6.1 Name: PIO Enable Register PIO_PER Addresses: 0xFFFFF200 (PIOA), 0xFFFFF400 (PIOB), 0xFFFFF600 (PIOC), 0xFFFFF800 (PIOD), 0xFFFFFA00 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Enable 0 = No effect.
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30.6.
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30.6.5 Name: PIO Output Disable Register PIO_ODR Addresses: 0xFFFFF214 (PIOA), 0xFFFFF414 (PIOB), 0xFFFFF614 (PIOC), 0xFFFFF814 (PIOD), 0xFFFFFA14 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Disable 0 = No effect.
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30.6.7 Name: PIO Input Filter Enable Register PIO_IFER Addresses: 0xFFFFF220 (PIOA), 0xFFFFF420 (PIOB), 0xFFFFF620 (PIOC), 0xFFFFF820 (PIOD), 0xFFFFFA20 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Enable 0 = No effect.
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30.6.
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30.6.11 Name: PIO Clear Output Data Register PIO_CODR Addresses: 0xFFFFF234 (PIOA), 0xFFFFF434 (PIOB), 0xFFFFF634 (PIOC), 0xFFFFF834 (PIOD), 0xFFFFFA34 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Clear Output Data 0 = No effect.
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30.6.13 Name: PIO Pin Data Status Register PIO_PDSR Addresses: 0xFFFFF23C (PIOA), 0xFFFFF43C (PIOB), 0xFFFFF63C (PIOC), 0xFFFFF83C (PIOD), 0xFFFFFA3C (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The I/O line is at level 0.
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30.6.15 Name: PIO Interrupt Disable Register PIO_IDR Addresses: 0xFFFFF244 (PIOA), 0xFFFFF444 (PIOB), 0xFFFFF644 (PIOC), 0xFFFFF844 (PIOD), 0xFFFFFA44 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0 = No effect.
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30.6.
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30.6.19 Name: PIO Multi-driver Disable Register PIO_MDDR Addresses: 0xFFFFF254 (PIOA), 0xFFFFF454 (PIOB), 0xFFFFF654 (PIOC), 0xFFFFF854 (PIOD), 0xFFFFFA54 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Disable. 0 = No effect.
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30.6.21 Name: PIO Pull Up Disable Register PIO_PUDR Addresses: 0xFFFFF260 (PIOA), 0xFFFFF460 (PIOB), 0xFFFFF660 (PIOC), 0xFFFFF860 (PIOD), 0xFFFFFA60 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Disable. 0 = No effect.
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30.6.23 Name: PIO Pull Up Status Register PIO_PUSR Addresses: 0xFFFFF268 (PIOA), 0xFFFFF468 (PIOB), 0xFFFFF668 (PIOC), 0xFFFFF868 (PIOD), 0xFFFFFA68 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status.
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30.6.25 Name: PIO Peripheral B Select Register PIO_BSR Addresses: 0xFFFFF274 (PIOA), 0xFFFFF474 (PIOB), 0xFFFFF674 (PIOC), 0xFFFFF874 (PIOD), 0xFFFFFA74 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral B Select. 0 = No effect.
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30.6.27 Name: PIO Output Write Enable Register PIO_OWER Addresses: 0xFFFFF2A0 (PIOA), 0xFFFFF4A0 (PIOB), 0xFFFFF6A0 (PIOC), 0xFFFFF8A0 (PIOD), 0xFFFFFAA0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Enable. 0 = No effect.
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30.6.29 Name: PIO Output Write Status Register PIO_OWSR Addresses: 0xFFFFF2A8 (PIOA), 0xFFFFF4A8 (PIOB), 0xFFFFF6A8 (PIOC), 0xFFFFF8A8 (PIOD), 0xFFFFFAA8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status.
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30.6.30 Name: PIO I/O Delay Register PIO_DELAYRx [x=0..3] Addresses: 0xFFFFF2C0 (PIOA), 0xFFFFF4C0 (PIOB), 0xFFFFF6C0 (PIOC), 0xFFFFF8C0 (PIOD), 0xFFFFFAC0 (PIOE) Access: Read-write Reset Value: See Figure 30-2 31 30 29 28 27 26 Delay7 23 22 21 20 19 18 Delay5 15 14 13 6 24 17 16 9 8 1 0 Delay4 12 11 10 Delay3 7 25 Delay6 Delay2 5 4 Delay1 3 2 Delay0 • Delay x: Gives the number of elements in the delay line associated to pad x.
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30.6.31 Name: PIO Write Protect Mode Register PIO_WPMR Addresses: 0xFFFFF2E4 (PIOA), 0xFFFFF4E4 (PIOB), 0xFFFFF6E4 (PIOC), 0xFFFFF8E4 (PIOD), 0xFFFFFAE4 (PIOE) Access: Read-write Reset Value: See Table 30-2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 — 6 — 5 — 4 — • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
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30.6.32 Name: PIO Write Protect Status Register PIO_WPSR Addresses: 0xFFFFF2E8 (PIOA), 0xFFFFF4E8 (PIOB), 0xFFFFF6E8 (PIOC), 0xFFFFF8E8 (PIOD), 0xFFFFFAE8 (PIOE) Access: Read-only Reset Value: See Table 30-2 31 — 30 — 29 — 28 — 23 22 21 20 27 — 26 — 25 — 24 — 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 — 6 — 5 — 4 — • WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the PIO_WPSR register.
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31. Universal Synchronous Asynchronous Receiver Transmitter (USART) 31.1 Description The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
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31.3 Block Diagram Figure 31-1. USART Block Diagram Peripheral DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS PMC MCK DIV SCK Baud Rate Generator MCK/DIV User Interface SLCK APB Table 31-1.
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31.4 Application Block Diagram Figure 31-2. Application Block Diagram IrLAP PPP Serial Driver Field Bus Driver EMV Driver IrDA Driver SPI Driver USART 31.5 RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers SPI Bus I/O Lines Description Table 31-2.
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31.6 Product Dependencies 31.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
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31.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Inter-rupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. Table 31-4. 31.7 Peripheral IDs Instance ID USART0 7 USART1 8 USART2 9 USART3 10 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications.
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– – – – – – – – – – – – – Processing of frames with up to 256 data bytes Response Data length can be configurable or defined automatically by the Identifier Self synchronization in Slave node configuration Automatic processing and verification of the “Synch Break” and the “Synch Field” The “Synch Break” is detected even if it is partially superimposed with a data byte Automatic Identifier parity calculation/sending and verification Parity sending and verification can be disabled Automatic Checksum calculat
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31.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
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31.7.1.2 Baud Rate Calculation Example Table 31-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 31-5. Baud Rate Example (OVER = 0) Source Clock Expected Baud Rate MHz Bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.
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SelectedClock Baudrate = ----------------------------------------------------------------FP⎞ ⎞ ⎛ 8 ( 2 – Over ) ⎛ CD + ------⎝ ⎝ 8 ⎠⎠ The modified architecture is presented below: Figure 31-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 16-bit Counter 2 3 glitch-free logic 1 0 FIDI >1 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC USCLKS = 3 Sampling Clock 31.7.1.
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• B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 31-6. Table 31-6. Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 31-7. Table 31-7.
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Figure 31-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 31.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR).
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Figure 31-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
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defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length. Figure 31-9 illustrates and defines the valid patterns.
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Figure 31-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd Command Sync start frame delimiter SFD Manchester encoded data DATA Txd Data Sync start frame delimiter 31.7.3.3 Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set.
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If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR.
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31.7.3.5 Manchester Decoder When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence.
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Figure 31-16. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported.
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Figure 31-17. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line Manchester decoder USART Receiver Manchester encoder USART Emitter ASK/FSK downstream transmitter Downstream Receiver PA RF filter Mod VCO control The USART module is configured as a Manchester encoder/decoder.
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Figure 31-19. FSK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 31.7.3.7 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit.
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Figure 31-21.
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31.7.3.9 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 490. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd.
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31.7.3.10 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
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Table 31-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 31-10. Maximum Timeguard Length Depending on Baud Rate Baud Rate Bit time Timeguard Bit/sec μs ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 31.7.3.
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Figure 31-24. Receiver Time-out Block Diagram TO Baud Rate Clock 1 D Q Clock 16-bit Time-out Counter 16-bit Value = STTTO Character Received Load Clear TIMEOUT 0 RETTO Table 31-11 gives the maximum time-out period for some standard baud rates. Table 31-11.
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Figure 31-25. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 31.7.3.14 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0.
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Figure 31-26. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 31.7.3.15 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR.
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Figure 31-28. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 RXDIS = 1 Write US_CR RTS RXBUFF Figure 31-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 31-29.
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or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value.
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Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. 31.7.4.5 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0.
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The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: • Disable TX and Enable RX • Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). • Receive data 31.7.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used.
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Table 31-13. IrDA Baud Rate Error (Continued) Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.
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31.7.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 31-36. Figure 31-36.
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ter Protocol, where one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address only one SPI Slave because it can generate only one NSS signal.
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• to obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least 4 times lower than the system clock. 31.7.7.3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR).
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Figure 31-38. SPI Transfer Format (CPHA=1, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 6 5 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master ->RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS Figure 31-39.
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31.7.7.5 Character Transmission The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
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31.7.8 LIN Mode The LIN Mode provides Master node and Slave node connectivity on a LIN bus. The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. The main properties of the LIN bus are: • Single Master/Multiple Slaves concept • Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as a pure state machine.
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31.7.8.5 Header Transmission (Master Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. So in Master node configuration, the frame handling starts with the sending of the header. The header is transmitted as soon as the identifier is written in the LIN Identifier register (US_LINIR). At this moment the flag TXRDY falls.
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31.7.8.6 Header Reception (Slave Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. In Slave node configuration, the frame handling starts with the reception of the header. The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break Field.
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31.7.8.7 Slave Node Synchronization The synchronization is done only in Slave node configuration. The procedure is based on time measurement between falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times. Figure 31-42. Synch Field Synch Field 8 Tbit 2 Tbit 2 Tbit 2 Tbit 2 Tbit Start bit Stop bit The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section 31.7.1).
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FTOL_UNSYNCH is the deviation of the real slave node clock from the nominal clock frequency. The LIN Standard imposes that it must not exceed ±15%. The LIN Standard imposes also that for communication between two nodes, their bit rate must not differ by more than ±2%. This means that the Baudrate_deviation must not exceed ±1%. It follows from that, a minimum value for the nominal clock frequency: ⎛ ⎞ ⎜ [ 0.
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During header transmission, all the bits of the IDCHR field of the LIN Identifier register (US_LINIR) are sent on the bus. During header reception, all the bits of the IDCHR field are updated with the received Identifier. 31.7.8.9 Node Action In function of the identifier, the node is concerned, or not, by the LIN response. Consequently, after sending or receiving the identifier, the USART must be configured. There are three possible configurations: • PUBLISH: the node sends the response.
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31.7.8.10 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1).
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31.7.8.12 Frame Slot Mode This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to TFrame_Maximum. If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to TFrame_Maximum.
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31.7.8.13 LIN Errors 31.7.8.14 Bit Error This error is generated when the USART is transmitting and if the transmitted value on the Tx line is different from the value sampled on the Rx line. If a bit error is detected, the transmission is aborted at the next byte border. 31.7.8.15 Inconsistent Synch Field Error This error is generated in Slave node configuration if the Synch Field character received is other than 0x55. 31.7.8.
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– Check the LIN errors • Case 3: NACT = IGNORE, the USART is not concerned by the response – Wait until LINTC in US_CSR rises – Check the LIN errors Figure 31-46. Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Checksum Data N TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 31-47.
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Figure 31-48. Master Node Configuration, NACT=IGNORE Frame slot = TFrame_Maximum Frame Break Response space Header Data3 Synch Protected Identifier Interframe space Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR LINTC 31.7.8.21 Slave Node Configuration • Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver. • Write USART_MODE in US_MR to select the LIN mode and the Slave Node configuration.
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Figure 31-49. Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 31-50. Slave Node Configuration, NACT = SUBSCRIBE Break Synch Protected Identifier Data 1 Data N-1 TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 31-51.
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31.7.8.23 Master Node Configuration The user can choose between two PDC modes by the PDCM bit in the LIN Mode register (US_LINMR): • PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the PDC in the Transmit Holding register US_THR (instead of the LIN Mode register US_LINMR). Because the PDC transfer size is limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FDIS are written.
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31.7.8.24 Slave Node Configuration In this configuration, the PDC transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (US_LINIR). The LIN mode must be written by the user in the LIN Mode register (US_LINMR). The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT=SUBSCRIBE). Figure 31-54.
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31.7.8.26 Bus Idle Time-out If the LIN bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. In the LIN 2.0 specification, this time-out is fixed at 4 seconds. In the LIN 1.3 specification, it is fixed at 25000 Tbits. In Slave Node configuration, the Receiver Time-out detects an idle condition on the RXD line.
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Figure 31-56. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 31.7.9.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 31-57. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 31-57. Local Loopback Mode Configuration RXD Receiver 1 Transmitter TXD 31.7.9.
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31.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 31-17.
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31.8.1 Name: USART Control Register US_CR Addresses: 0xFFF8C000 (0), 0xFFF90000 (1), 0xFFF94000 (2), 0xFFF98000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS/RCS 18 RTSEN/FCS 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect.
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• RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR, LINBE, LINSFE, LINIPE, LINCE, LINSNRE and RXBRK in US_CSR. • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect.
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• RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select – If USART does not operate in SPI Master Mode (USART_MODE ≠ 0xE): 0: No effect. 1: Drives the pin RTS to 1. – If USART operates in SPI Master Mode (USART_MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin). • LINABT: Abort LIN Transmission 0: No effect. 1: Abort the current LIN transmission. • LINWKUP: Send LIN Wakeup Signal 0: No effect: 1: Sends a wakeup signal on the LIN bus.
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31.8.
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• CHRL: Character Length. CHRL Character Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits • SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase – If USART does not operate in SPI Mode (USART_MODE is ≠ 0xE and 0xF): SYNC = 0: USART operates in Asynchronous Mode. SYNC = 1: USART operates in Synchronous Mode. – If USART operates in SPI Mode (USART_MODE = 0xE or 0xF): CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
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• MSBF/CPOL: Bit Order or SPI Clock Polarity – If USART does not operate in SPI Mode (USART_MODE ≠ 0xE and 0xF): MSBF = 0: Least Significant Bit is sent/received first. MSBF = 1: Most Significant Bit is sent/received first. – If USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF): CPOL = 0: The inactive state value of SPCK is logic level zero. CPOL = 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK).
PAGE 528
1: Manchester Encoder/Decoder are enabled. • MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. • ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit.
PAGE 529
31.8.
PAGE 530
• LINBE: LIN Bus Error Interrupt Enable • LINISFE: LIN Inconsistent Synch Field Error Interrupt Enable • LINIPE: LIN Identifier Parity Interrupt Enable • LINCE: LIN Checksum Error Interrupt Enable • LINSNRE: LIN Slave Not Responding Error Interrupt Enable SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 530
PAGE 531
31.8.
PAGE 532
• LINBE: LIN Bus Error Interrupt Disable • LINISFE: LIN Inconsistent Synch Field Error Interrupt Disable • LINIPE: LIN Identifier Parity Interrupt Disable • LINCE: LIN Checksum Error Interrupt Disable • LINSNRE: LIN Slave Not Responding Error Interrupt Disable SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 532
PAGE 533
31.8.
PAGE 534
• LINBE: LIN Bus Error Interrupt Mask • LINISFE: LIN Inconsistent Synch Field Error Interrupt Mask • LINIPE: LIN Identifier Parity Interrupt Mask • LINCE: LIN Checksum Error Interrupt Mask • LINSNRE: LIN Slave Not Responding Error Interrupt Mask SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 534
PAGE 535
31.8.
PAGE 536
• FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
PAGE 537
– 1:At least one LIN Identifier has been sent since the last RSTSTA.If USART operates in LIN Slave Mode (USART_MODE = 0xB): 0: No LIN Identifier has been received since the last RSTSTA. 1:At least one LIN Identifier has been received since the last RSTSTA • LINTC: LIN Transfer Completed 0: The USART is idle or a LIN transfer is ongoing. 1: A LIN transfer has been completed since the last RSTSTA.
PAGE 538
31.8.7 Name: USART Receive Holding Register US_RHR Addresses: 0xFFF8C018 (0), 0xFFF90018 (1), 0xFFF94018 (2), 0xFFF98018 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
PAGE 539
31.8.8 Name: USART Transmit Holding Register US_THR Addresses: 0xFFF8C01C (0), 0xFFF9001C (1), 0xFFF9401C (2), 0xFFF9801C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
PAGE 540
31.8.
PAGE 541
31.8.10 Name: USART Receiver Time-out Register US_RTOR Addresses: 0xFFF8C024 (0), 0xFFF90024 (1), 0xFFF94024 (2), 0xFFF98024 (3) Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 131071: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
PAGE 542
31.8.11 Name: USART Transmitter Timeguard Register US_TTGR Addresses: 0xFFF8C028 (0), 0xFFF90028 (1), 0xFFF94028 (2), 0xFFF98028 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
PAGE 543
31.8.12 Name: USART FI DI RATIO Register US_FIDI Addresses: 0xFFF8C040 (0), 0xFFF90040 (1), 0xFFF94040 (2), 0xFFF98040 (3) Access: Read-write Reset Value: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
PAGE 544
31.8.13 Name: USART Number of Errors Register US_NER Addresses: 0xFFF8C044 (0), 0xFFF90044 (1), 0xFFF94044 (2), 0xFFF98044 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
PAGE 545
31.8.14 Name: USART IrDA FILTER Register US_IF Addresses: 0xFFF8C04C (0), 0xFFF9004C (1), 0xFFF9404C (2), 0xFFF9804C (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
PAGE 546
31.8.
PAGE 547
• RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled.
PAGE 548
31.8.16 Name: USART3 LIN Mode Register US_LINMR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 0 NACT • NACT: LIN Node Action NACT Mode Description 0 0 PUBLISH: The USART transmits the response. 0 1 SUBSCRIBE: The USART receives the response. 1 0 IGNORE: The USART does not transmit and does not receive the response.
PAGE 549
1: setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. • DLC: Data Length Control 0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes. • PDCM: PDC Mode 0: The LIN mode register US_LINMR is not written by the PDC. 1: The LIN mode register US_LINMR (excepting that flag) is written by the PDC.
PAGE 550
31.8.17 Name: USART3 LIN Identifier Register US_LINIR Access: Read-write or Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR • IDCHR: Identifier Character If USART_MODE=0xA (Master node configuration): IDCHR is Read-write and its value is the Identifier character to be transmitted.
PAGE 551
32. Two-wire Interface (TWI) 32.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
PAGE 552
32.3 List of Abbreviations Table 32-2. 32.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 32-1.
PAGE 553
32.5 Application Block Diagram Figure 32-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 32.5.1 I/O Lines Description Table 32-3. I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 32.6 Product Dependencies 32.6.
PAGE 554
32.6.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI. Table 32-5. Peripheral IDs Instance ID TWI0 12 TWI1 13 32.7 Functional Description 32.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 32-4).
PAGE 555
32.8 Master Mode 32.8.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 32.8.2 Application Block Diagram Figure 32-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 32.8.
PAGE 556
See Figure 32-6, Figure 32-7, and Figure 32-8. Figure 32-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) S TWD DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 32-7.
PAGE 557
Figure 32-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) 32.8.5 Write THR (Data n+2) Last data sent Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7bit slave address to notify the slave device.
PAGE 558
Figure 32-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read 32.8.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 32.8.6.
PAGE 559
Figure 32-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address S TWD DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two bytes internal address S TWD DADR P One byte internal address S TWD DADR P Figure 32-12.
PAGE 560
32.8.7 SMBUS Quick Command (Master Mode Only) The TWI interface can perform a Quick Command: 1. Configure the master mode (DADR, CKDIV, etc.). 2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent. 3. Start the transfer by setting the QUICK bit in the TWI_CR. Figure 32-14. SMBUS Quick Command TWD S DADR R/W A P TXCOMP TXRDY Write QUICK command in TWI_CR 32.8.
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Figure 32-15.
PAGE 562
Figure 32-16.
PAGE 563
Figure 32-17.
PAGE 564
Figure 32-18.
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Figure 32-19.
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Figure 32-20.
PAGE 567
32.9 Multi-master Mode 32.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
PAGE 568
Figure 32-21. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 32-22.
PAGE 569
Figure 32-23.
PAGE 570
32.10 Slave Mode 32.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 32.10.2 Application Block Diagram Figure 32-24. Slave Mode Typical Application Block Diagram VDD R Master Host with TWI Interface 32.10.
PAGE 571
32.10.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 32-26 on page 573. 32.10.4.
PAGE 572
32.10.5 Data Transfer 32.10.5.1 Read Operation The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register.
PAGE 573
Figure 32-26. Write Access Ordered by a Master SADR does not match, TWI answers with a NACK S TWD ADR W NA DATA NA SADR matches, TWI answers with an ACK P/S/Sr SADR W A DATA Read RHR A A DATA NA S/Sr RXRDY SVACC SVREAD has to be taken into account only while SVACC is active SVREAD EOSVACC Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read. 32.10.5.
PAGE 574
32.10.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. 32.10.5.5 Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
PAGE 575
32.10.5.6 Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 32-29 on page 575 describes the clock synchronization in Read mode. Figure 32-29.
PAGE 576
32.10.5.7 Reversal after a Repeated Start 32.10.5.8 Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 32-30 on page 576 describes the repeated start + reversal from Read to Write mode. Figure 32-30.
PAGE 577
32.10.6 Read Write Flowcharts The flowchart shown in Figure 32-32 on page 577 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 32-32.
PAGE 578
32.11 Two-wire Interface (TWI) User Interface Table 32-6.
PAGE 579
32.11.1 Name: TWI Control Register TWI_CR Addresses: 0xFFF84000 (0), 0xFFF88000 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
PAGE 580
• SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0 = No effect.
PAGE 581
32.11.
PAGE 582
32.11.3 Name: TWI Slave Mode Register TWI_SMR Addresses: 0xFFF84008 (0), 0xFFF88008 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.
PAGE 583
32.11.4 Name: TWI Internal Address Register TWI_IADR Addresses: 0xFFF8400C (0), 0xFFF8800C (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
PAGE 584
32.11.5 Name: TWI Clock Waveform Generator Register TWI_CWGR Addresses: 0xFFF84010 (0), 0xFFF88010 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode.
PAGE 585
32.11.6 Name: TWI Status Register TWI_SR Addresses: 0xFFF84020 (0), 0xFFF88020 (1) Access: Read-only Reset: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame.
PAGE 586
TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it.
PAGE 587
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. • ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration.
PAGE 588
32.11.
PAGE 589
32.11.
PAGE 590
32.11.
PAGE 591
32.11.
PAGE 592
32.11.
PAGE 593
33. Synchronous Serial Controller (SSC) 33.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
PAGE 594
33.3 Block Diagram Figure 33-1.
PAGE 595
Figure 33-2. Block Diagram System Bus APB Bridge DMA Peripheral Bus TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 33.4 Application Block Diagram Figure 33-3.
PAGE 596
33.5 Pin Name List Table 33-1. I/O Lines Description Pin Name Pin Description Type RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 33.6 Product Dependencies 33.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
PAGE 597
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and Table 33-3. Peripheral IDs Instance ID SSC0 16 SSC1 17 unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register.
PAGE 598
33.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
PAGE 599
33.7.
PAGE 600
33.7.1.1 Clock Divider Figure 33-5. Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive.
PAGE 601
Figure 33-7. Transmitter Clock Management TK (pin) Clock Output Tri_state Controller MUX Receiver Clock Divider Clock Data Transfer CKO CKS INV MUX Tri-state Controller CKI CKG Transmitter Clock 33.7.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register).
PAGE 602
– Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: – Master Clock divided by 6 if Transmit Frame Synchro is input – Master Clock divided by 2 if Transmit Frame Synchro is output 33.7.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR).
PAGE 603
The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register.
PAGE 604
Figure 33-11. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) TD (Output) B1 BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 33-12.
PAGE 605
33.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported.
PAGE 606
compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. 33.7.
PAGE 607
Table 33-5.
PAGE 608
Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 33-16. Receive Frame Format in Continuous Mode Start = Enable Receiver Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN RD Note: 1. STTDLY is set to 0. 33.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR.
PAGE 609
Figure 33-18.
PAGE 610
33.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 33-19. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB MSB Right Channel Left Channel Figure 33-20.
PAGE 611
Figure 33-21.
PAGE 612
33.9 Synchronous Serial Controller (SSC) User Interface Table 33-6.
PAGE 613
33.9.1 Name: SSC Control Register SSC_CR: Addresses: 0xFFF9C000 (0), 0xFFFA0000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive.
PAGE 614
33.9.2 Name: SSC Clock Mode Register SSC_CMR Addresses: 0xFFF9C004 (0), 0xFFFA0004 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DIV 3 2 DIV • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
PAGE 615
33.9.
PAGE 616
• CKG: Receive Clock Gating Selection CKG Receive Clock Gating 0x0 None, continuous clock 0x1 Receive Clock enabled only if RF Low 0x2 Receive Clock enabled only if RF High 0x3 Reserved • START: Receive Start Selection START Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
PAGE 617
33.9.4 Name: SSC Receive Frame Mode Register SSC_RFMR Addresses: 0xFFF9C014 (0), 0xFFFA0014 (1) Access: Read-write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT FSLEN_EXT 23 – 22 15 – 7 MSBF 28 27 – 26 – 25 – 24 FSEDGE 21 FSOS 20 19 18 17 16 14 – 13 – 12 – 11 9 8 6 – 5 LOOP 4 3 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
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• FSOS: Receive Frame Sync Output Selection FSOS Selected Receive Frame Sync Signal RF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Input-only Reserved Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
PAGE 619
33.9.
PAGE 620
• CKG: Transmit Clock Gating Selection CKG Transmit Clock Gating 0x0 None, continuous clock 0x1 Transmit Clock enabled only if TF Low 0x2 Transmit Clock enabled only if TF High 0x3 Reserved • START: Transmit Start Selection START Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
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33.9.6 Name: SSC Transmit Frame Mode Register SSC_TFMR Addresses: 0xFFF9C01C (0), 0xFFFA001C (1) Access: Read-write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT FSLEN_EXT 23 FSDEN 22 15 – 7 MSBF 28 27 – 26 – 25 – 24 FSEDGE 21 FSOS 20 19 18 17 16 14 – 13 – 12 – 11 9 8 6 – 5 DATDEF 4 3 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
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• FSOS: Transmit Frame Sync Output Selection FSOS Selected Transmit Frame Sync Signal TF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Input-only Reserved Undefined • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal.
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33.9.7 Name: SSC Receive Holding Register SSC_RHR Addresses: 0xFFF9C020 (0), 0xFFFA0020 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 33.9.
PAGE 624
33.9.9 Name: SSC Receive Synchronization Holding Register SSC_RSHR Addresses: 0xFFF9C030 (0), 0xFFFA0030 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT • RSDAT: Receive Synchronization Data 33.9.
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33.9.
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33.9.
PAGE 627
33.9.13 Name: SSC Status Register SSC_SR Addresses: 0xFFF9C040 (0), 0xFFFA0040 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.
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• RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register.
PAGE 629
33.9.14 Name: SSC Interrupt Enable Register SSC_IER Addresses: 0xFFF9C044 (0), 0xFFFA0044 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0 = 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect.
PAGE 630
1 = Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt.
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33.9.15 Name: SSC Interrupt Disable Register SSC_IDR Addresses: 0xFFF9C048 (0), 0xFFFA0048 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect.
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1 = Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt.
PAGE 633
33.9.16 Name: SSC Interrupt Mask Register SSC_IMR Addresses: 0xFFF9C04C (0), 0xFFFA004C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.
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1 = The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled. • RXSYN: Rx Sync Interrupt Mask 0 = The Rx Sync Interrupt is disabled. 1 = The Rx Sync Interrupt is enabled.
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34. Timer Counter (TC) 34.1 Description The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
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34.3 Block Diagram Figure 34-1.
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34.4 Pin Name List Table 34-3. TC pin list Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O 34.5 Product Dependencies 34.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 34-4.
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34.6 Functional Description 34.6.1 TC Description The three channels of the Timer Counter are independent and identical in operation . The registers for channel programming are listed in Table 34-5 on page 650. 34.6.2 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock.
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Figure 34-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK2 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 34-3.
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34.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 34-4. • • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
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The following triggers are common to both modes: • • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.
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TIOA TIOB SYNC XC2 XC1 XC0 MTIOA MTIOB TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG CLKI Edge Detector LDRA S R OVF If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q LDBSTOP R S CLKEN Edge Detector LDRB Capture Register A Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR Timer/Counter Channel ABETRG BURST TCCLKS Compare RC = Register C COVFS INT Figure 34-5.
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34.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
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TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TCCLKS TIOB MTIOB TIOA MTIOA Figu
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34.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 34-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 34-8. RC Compare cannot be programmed to generate a trigger in this configuration.
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34.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 34-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 34-10.
PAGE 647
34.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 34-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 34-12.
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34.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 34-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 34-14.
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34.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
PAGE 650
34.7 Timer Counter (TC) User Interface Table 34-5.
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34.7.1 Name: TC Block Control Register TC_BCR Addresses: 0xFFF7C0C0 (0), 0xFFFD40C0 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SYNC • SYNC: Synchro Command 0 = no effect. 1 = asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
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34.7.
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34.7.3 Name: TC Channel Control Register TC_CCRx [x=0..2] Addresses: 0xFFF7C000 (0)[0], 0xFFF7C040 (0)[1], 0xFFF7C080 (0)[2], 0xFFFD4000 (1)[0], 0xFFFD4040 (1)[1], 0xFFFD4080 (1)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SWTRG 1 CLKDIS 0 CLKEN • CLKEN: Counter Clock Enable Command 0 = no effect. 1 = enables the clock if CLKDIS is not 1.
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34.7.4 Name: TC Channel Mode Register: Capture Mode TC_CMRx [x=0..
PAGE 655
0 = counter clock is not disabled when RB loading occurs. 1 = counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock.
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34.7.5 Name: TC Channel Mode Register: Waveform Mode TC_CMRx [x=0..
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1 = counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • EEVT: External Event Selection EEVT Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
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• ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPC: RC Compare Effect on TIOB BCPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle SAM9M1
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• BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 659
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34.7.6 Name: TC Counter Value Register TC_CVx [x=0..2] Addresses: 0xFFF7C010 (0)[0], 0xFFF7C050 (0)[1], 0xFFF7C090 (0)[2], 0xFFFD4010 (1)[0] 0xFFFD4050 (1)[1], 0xFFFD4090 (1)[2] Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time. 34.7.7 Name: TC Register A TC_RAx [x=0..
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34.7.8 Name: TC Register B TC_RBx [x=0..2] Addresses: 0xFFF7C018 (0)[0], 0xFFF7C058 (0)[1], 0xFFF7C098 (0)[2], 0xFFFD4018 (1)[0], 0xFFFD4058 (1)[1], 0xFFFD4098 (1)[2] Access: Read-only if WAVE = 0, Read-write if WAVE = 1 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time. 34.7.9 Name: TC Register C TC_RCx [x=0..
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34.7.10 Name: TC Status Register TC_SRx [x=0..
PAGE 663
• CLKSTA: Clock Enabling Status 0 = clock is disabled. 1 = clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high.
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34.7.11 Name: TC Interrupt Enable Register TC_IERx [x=0..2] Addresses: 0xFFF7C024 (0)[0], 0xFFF7C064 (0)[1], 0xFFF7C0A4 (0)[2], 0xFFFD4024 (1)[0], 0xFFFD4064 (1)[1], 0xFFFD40A4 (1)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0 = no effect. 1 = enables the Counter Overflow Interrupt.
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34.7.12 Name: TC Interrupt Disable Register TC_IDRx [x=0..2] Addresses: 0xFFF7C028 (0)[0], 0xFFF7C068 (0)[1], 0xFFF7C0A8 (0)[2], 0xFFFD4028 (1)[0], 0xFFFD4068 (1)[1], 0xFFFD40A8 (1)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0 = no effect. 1 = disables the Counter Overflow Interrupt.
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34.7.13 Name: TC Interrupt Mask Register TC_IMRx [x=0..2] Addresses: 0xFFF7C02C (0)[0], 0xFFF7C06C (0)[1], 0xFFF7C0AC (0)[2], 0xFFFD402C (1)[0], 0xFFFD406C (1)[1], 0xFFFD40AC (1)[2] Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0 = the Counter Overflow Interrupt is disabled.
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35. High Speed MultiMedia Card Interface (HSMCI) 35.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
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35.3 Block Diagram Figure 35-1. Block Diagram APB Bridge DMAC APB MCCK (1) MCCDA HSMCI Interface PMC MCK (1) MCDA0 (1) PIO MCDA1 (1) MCDA2 (1) MCDA3 (1) MCDA4 (1) MCDA5 (1) MCDA6 (1) Interrupt Control MCDA7 (1) HSMCI Interrupt Note: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy.
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35.4 Application Block Diagram Figure 35-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 1 2 3 4 5 6 7 1 2 3 4 5 6 78 9 9 1011 1213 8 MMC 35.5 SDCard Pin Name List Table 35-1. I/O Lines Description Pin Name(2) Pin Description Type(1) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0 - MCDA7 Data 0..7 of Slot A I/O/PP DAT[0..
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35.6 Product Dependencies 35.6.1 I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins. Table 35-2.
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35.7 Bus Topology Figure 35-3. High Speed MultiMedia Memory Card Bus Topology 1 2 3 4 5 6 7 9 1011 1213 8 MMC The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 35-4.
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Figure 35-4. MMC Bus Connections (One Slot) HSMCI MCDA0 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 1011 9 1011 9 1011 1213 8 MMC1 Note: 1213 8 MMC2 1213 8 MMC3 When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Figure 35-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 35-5. Table 35-5.
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MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Figure 35-6. SD Card Bus Connections with One Slot Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits.
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35.8.1 Command - Response Operation After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR Control Register. The PWSEN bit saves power by dividing the HSMCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
PAGE 675
As soon as the command register is written, then the status bit CMDRDY in the status register (HSMCI_SR) is cleared. It is released and the end of the card response. If the command requires a response, it can be read in the HSMCI response register (HSMCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The HSMCI embeds an error detection to prevent any corrupted data during the transfer.
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35.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the DMA Controller. In all cases, the block length (BLKLEN field) must be defined either in the mode register HSMCI_MR, or in the Block Register HSMCI_BLKR.
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Figure 35-8.
PAGE 678
35.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing nonmultiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit DMAEN in the HSMCI_DMA register enables DMA transfer. The following flowchart (Figure 35-9) shows how to write a single block with or without use of DMA facilities.
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Figure 35-9.
PAGE 680
The following flowchart (Figure 35-10) shows how to manage read multiple block and write multiple block transfers with the DMA Controller. Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (HSMCI_IMR). Figure 35-10.
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35.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller 1. Wait until the current command execution has successfully terminated. a. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI configuration register with block_length value. 4. Program HSMCI_DMA register with the following fields: – OFFSET field with dma_offset.
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35.8.6 READ_SINGLE_BLOCK Operation using DMA Controller 35.8.6.1 1. 2. 3. 4. 5. Block Length is Multiple of 4 Wait until the current command execution has successfully completed. a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR. Program the block length in the card. This value defines the value block_length. Program the block length in the HSMCI configuration register with block_length value. Set RDPROOF bit in HSMCI_MR to avoid overflow.
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35.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0) In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to use only WORD AHB access. When the block length is no longer a multiple of 4 this is no longer true. The DMA controller is programmed to copy exactly the block length number of bytes using 2 transfer descriptors. 1. Use the previous step until READ_SINGLE_BLOCK then 2.
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–SRC_WIDTH is set to BYTE. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). n. Program LLI_B.DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR –SRC_INCR is set to INCR –FC field is programmed with peripheral to memory flow control mode. –Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0.
PAGE 685
–FC field is programmed with peripheral to memory flow control mode. –both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled) –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously. h. Program DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –SRC_H2SEL is set to true to enable hardware handshaking on the destination.
PAGE 686
–SRC_DSCR is set to 1 (source address is contiguous). –FC field is programmed with memory to peripheral flow control mode. –Both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled). –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA Controller is able to prefetch data and write HSMCI simultaneously. h. Program LLI(n).DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO.
PAGE 687
a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register. c. Program the channel registers in the Memory with the first descriptor. This descriptor will be word oriented. This descriptor is referred to as LLI_W(n), standing for LLI word oriented transfer for block n. d. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address. e.
PAGE 688
a. Read the channel register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the DMAC_EBCISR register. c. For every block of data repeat the following procedure: d. Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented. This descriptor is referred to as LLI_W(n) standing for LLI word oriented transfer for block n. e. The LLI_W(n).
PAGE 689
– SRC_INCR is set to INCR. – FC field is programmed with peripheral to memory flow control mode. – Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0. – DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously. p. Program LLI_B(n).
PAGE 690
g. Program LLI_W(n).DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR –SRC_INCR is set to INCR –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0. (descriptor fetch is enabled for the SRC) –DST_DSCR is set to TRUE. (descriptor fetch is disabled for the DST) –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously. h. Program LLI_W(n).
PAGE 691
35.9.1 SDIO Data Transfer Type SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The TRTYP field in the HSMCI Command Register (HSMCI_CMDR) allows to choose between SDIO Byte or SDIO Block transfer. The number of bytes/blocks to transfer is set through the BCNT field in the HSMCI Block Register (HSMCI_BLKR).
PAGE 692
35.10.4 CE-ATA Error Recovery Several methods of ATA command failure may occur, including: • No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60). • CRC is invalid for an MMC command or response. • CRC16 is invalid for an MMC data packet. • ATA Status register reflects an error by setting the ERR bit to one. • The command completion signal does not arrive within a host specified time out period. Error conditions are expected to happen infrequently.
PAGE 693
35.11.2 Boot Procedure, DMA Mode 1. Configure the HSMCI data bus width by programming SDCBUS Field in the HSMCI_SDCR register. The BOOT_BUS_WIDTH field in the device Extended CSD register must be set accordingly. 2. Set the byte count to 512 bytes and the block count to the desired number of blocks by writing BLKLEN and BCNT fields of the HSMCI_BLKR Register. 3. Enable DMA transfer in the HSMCI_DMA register. 4.
PAGE 694
35.12 HSMCI Transfer Done Timings 35.12.1 Definition The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished. 35.12.2 Read Access During a read access, the XFRDONE flag behaves as shown in Figure 35-11. Figure 35-11. XFRDONE During a Read Access CMD line MCI read CMD Card response The CMDRDY flag is released 8 tbit after the end of the card response.
PAGE 695
35.12.3 Write Access During a write access, the XFRDONE flag behaves as shown in Figure 35-12. Figure 35-12. XFRDONE During a Write Access CMD line MCI writeCMD CMDRDY flag Card response The CMDRDY flag is released 8 tbit after the end of the card response.
PAGE 696
35.13 MultiMedia Card Interface (MCI) User Interface Table 35-8.
PAGE 697
35.13.1 Name: HSMCI Control Register HSMCI_CR Addresses: 0xFFF80000 (0), 0xFFFD0000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 PWSDIS 2 PWSEN 1 HSMCIDIS 0 MCIEN • MCIEN: Multi-Media Interface Enable 0 = No effect. 1 = Enables the Multi-Media Interface if MCDIS is 0. • MCIDIS: Multi-Media Interface Disable 0 = No effect.
PAGE 698
35.13.2 Name: HSMCI Mode Register HSMCI_MR Addresses: 0xFFF80004 (0), 0xFFFD0004 (1) Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 BLKLEN 23 22 21 20 BLKLEN 15 – 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 3 2 1 0 CLKDIV • CLKDIV: Clock Divider High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
PAGE 699
• BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the HSMCI Block Register (HSMCI_BLKR). Bits 16 and 17 must be set to 0 if FBYTE is disabled. Note: In SDIO Byte mode, BLKLEN field is not used.
PAGE 700
35.13.3 Name: HSMCI Data Timeout Register HSMCI_DTOR Addresses: 0xFFF80008 (0), 0xFFFD0008 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 DTOMUL 4 3 2 1 0 DTOCYC • DTOCYC: Data Timeout Cycle Number • DTOMUL: Data Timeout Multiplier These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers.
PAGE 701
35.13.4 Name: HSMCI SDCard/SDIO Register HSMCI_SDCR Addresses: 0xFFF8000C (0), 0xFFFD000C (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 5 – 4 – 3 – 2 – 1 7 SDCBUS 0 SDCSEL • SDCSEL: SDCard/SDIO Slot SDCSEL SDCard/SDIO Slot 0 0 Slot A is selected.
PAGE 702
35.13.
PAGE 703
35.13.6 Name: HSMCI Command Register HSMCI_CMDR Addresses: 0xFFF80014 (0), 0xFFFD0014 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 BOOT_ACK 26 ATACS 25 23 – 22 – 21 20 TRTYP 19 18 TRDIR 17 15 – 14 – 13 – 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 6 5 4 3 2 1 0 7 RSPTYP 24 IOSPCMD 16 TRCMD CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writeable by an interrupt response (field SPCMD).
PAGE 704
SPCMD Command 1 0 1 Interrupt response: Corresponds to the Interrupt Mode (CMD40). 1 1 0 Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. 1 1 1 End Boot Operation. This command allows the host processor to terminate the boot operation mode.
PAGE 705
• IOSPCMD: SDIO Special Command IOSPCMD SDIO Special Command Type 0 0 Not a SDIO Special Command 0 1 SDIO Suspend Command 1 0 SDIO Resume Command 1 1 Reserved • ATACS: ATA with Command Completion Signal 0 = Normal operation mode. 1 = This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). • BOOT_ACK: Boot Operation Acknowledge. The master can choose to receive the boot acknowledge from the slave when a Boot Request command is issued.
PAGE 706
35.13.7 Name: HSMCI Block Register HSMCI_BLKR Addresses: 0xFFF80018 (0), 0xFFFD0018 (1) Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer.
PAGE 707
35.13.
PAGE 708
35.13.9 Name: HSMCI Response Register HSMCI_RSPR Addresses: 0xFFF80020 (0), 0xFFFD0020 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response. 35.13.
PAGE 709
35.13.
PAGE 710
35.13.12 HSMCI Status Register Name: HSMCI_SR Addresses: 0xFFF80040 (0), 0xFFFD0040 (1) Access: Read-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 14 13 12 11 10 9 – – CSRCV SDIOWAIT – – – 8 MCI_SDIOIR QA 7 – 6 – 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY • CMDRDY: Command Ready 0 = A command is in progress. 1 = The last command has been sent.
PAGE 711
0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response. 1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior. For all the read operations, the NOTBUSY flag is cleared at the end of the host command.
PAGE 712
• DCRCE: Data CRC Error 0 = No error. 1 = A CRC16 error has been detected in the last data block. Cleared by reading in the HSMCI_SR register. • DTOE: Data Time-out Error 0 = No error. 1 = The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the HSMCI_SR register. • CSTOE: Completion Signal Time-out Error 0 = No error. 1 = The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading in the HSMCI_SR register.
PAGE 713
• UNRE: Underrun 0 = No error. 1 = At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1. When FERRCTRL in HSMCI_CFG is set to 1, UNRE becomes reset after read.
PAGE 714
35.13.
PAGE 715
• ACKRCV: Boot Acknowledge Interrupt Enable • ACKRCVE: Boot Acknowledge Error Interrupt Enable • OVRE: Overrun Interrupt Enable • UNRE: Underrun Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
PAGE 716
35.13.
PAGE 717
• ACKRCV: Boot Acknowledge Interrupt Disable • ACKRCVE: Boot Acknowledge Error Interrupt Disable • OVRE: Overrun Interrupt Disable • UNRE: Underrun Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
PAGE 718
35.13.
PAGE 719
• ACKRCV: Boot Operation Acknowledge Received Interrupt Mask • ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask • OVRE: Overrun Interrupt Mask • UNRE: Underrun Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
PAGE 720
35.13.16 HSMCI DMA Configuration Register Name: HSMCI_DMA Addresses: 0xFFF80050 (0), 0xFFFD0050 (1) Access: Read-write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 ROPT 11 – 10 – 9 – 8 DMAEN 7 – 6 – 5 4 3 – 2 – 1 CHKSIZE 0 OFFSET • OFFSET: DMA Write Buffer Offset This field indicates the number of discarded bytes when the DMA writes the first word of the transfer.
PAGE 721
35.13.17 HSMCI Configuration Register Name: HSMCI_CFG Addresses: 0xFFF80054 (0), 0xFFFD0054 (1) Access: Read-write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LSYNC 11 – 10 – 9 – 8 HSMODE 7 – 6 – 5 – 4 FERRCTRL 3 – 2 – 1 – 0 FIFOMODE • FIFOMODE: HSMCI Internal FIFO control mode 0 = A write transfer starts when a sufficient amount of data is written into the FIFO.
PAGE 722
35.13.18 HSMCI Write Protect Mode Register Name: HSMCI_WPMR Addresses: 0xFFF800E4 (0), 0xFFFD00E4 (1) Access: Read-write 31 30 29 28 27 WP_KEY (0x4D => “M”) 26 25 24 23 22 21 20 19 WP_KEY (0x43 => C”) 18 17 16 15 14 13 12 11 WP_KEY (0x49 => “I”) 10 9 8 7 6 5 2 1 0 WP_EN 4 3 • WP_EN: Write Protection Enable 0 = Disables the Write Protection if WP_KEY corresponds. 1 = Enables the Write Protection if WP_KEY corresponds.
PAGE 723
35.13.
PAGE 724
35.13.
PAGE 725
36. Ethernet MAC 10/100 (EMAC) 36.1 Description The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal.
PAGE 726
36.3 Block Diagram Figure 36-1.
PAGE 727
36.4 Functional Description The MACB has several clock domains: • System bus clock (AHB and APB): DMA and register blocks • Transmit clock: transmit block • Receive clock: receive and address checker block The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5 MHZ at 10 Mbps). Figure 36-1 illustrates the different blocks of the EMAC module.
PAGE 728
Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when the FIFO contains four words and has space for 28 more. For transmit, a bus request is generated when there is space for four words, or when there is space for 27 words if the next transfer is to be only one or two words. Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (112 bytes) of data.
PAGE 729
Table 36-1. Receive Buffer Descriptor Entry (Continued) Bit Function 19:17 VLAN priority (only valid if bit 21 is set) 16 Concatenation format indicator (CFI) bit (only valid if bit 21 is set) 15 End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14. 14 Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame.
PAGE 730
If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer not available bit in the receive status register and triggers an interrupt.
PAGE 731
– there is a transmit error such as too many retries or a transmit underrun. To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take effect until any ongoing transmit finishes. If a collision occurs during transmission of a multi-buffer frame, transmission automatically restarts from the first buffer of the frame. If a “used” bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error.
PAGE 732
After the first collision, 1 bit is used, after the second 2, and so on up to 10. Above 10, all 10 bits are used. An error is indicated and no further attempts are made if 16 attempts cause collisions. If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and the tx_er signal is asserted. For a properly configured system, this should never happen.
PAGE 733
36.4.6 Address Checking Block The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory. Whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame’s destination address. In this implementation of the EMAC, the frame’s source address is not checked.
PAGE 734
• Base address + 0xB8 0x00004321 36.4.7 Broadcast Address The broadcast address of 0xFFFFFFFFFFFF is recognized if the ‘no broadcast’ bit in the network configuration register is zero. 36.4.8 Hash Addressing The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top.
PAGE 735
36.4.11 VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 36-4. 802.1Q VLAN Tag TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits 0x8100 First 3 bits priority, then CFI bit, last 12 bits VID The VLAN tag is inserted at the 13th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame.
PAGE 736
The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved value of 0x0000 for the Wake-on-LAN target address value does not cause an ARP request event, even if matched by the frame.
PAGE 737
Table 36-5. Pin Configuration ERXCK ERXCK: Receive Clock ETXEN ETXEN: Transmit Enable ETXEN: Transmit Enable ETX0 - ETX3: 4-bit Transmit Data ETX0 - ETX1: 2-bit Transmit Data ETX0-ETX3 ETXER ETXER: Transmit Error The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It uses 2 bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1).
PAGE 738
36.5 36.5.1 Programming Interface Initialization 36.5.1.1 Configuration Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document. To change loop-back mode, the following sequence of operations must be followed: 1. Write to network control register to disable transmit and receive circuits. 2.
PAGE 739
36.5.1.3 Transmit Buffer List Transmit data is read from areas of data (the buffers) in system memory These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries (as defined in Table 36-2 on page 731) that points to this data structure. To create this list of buffers: 1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory.
PAGE 740
• if it matches the hash address function. • if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed. • if the EMAC is configured to copy all frames. The register receive buffer queue pointer points to the next entry (see Table 36-1 on page 728) and the EMAC uses this as the address in system memory to write the frame to.
PAGE 741
36.6 Ethernet MAC 10/100 (EMAC) User Interface Table 36-6.
PAGE 742
Table 36-6.
PAGE 743
36.6.1 Name: Network Control Register EMAC_NCR Address: 0xFFFBC000 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TE 2 RE 1 LLB 0 LB • LB: LoopBack Asserts the loopback signal to the PHY. • LLB: Loopback local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4.
PAGE 744
• TSTART: Start transmission Writing one to this bit starts transmission. • THALT: Transmit halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
PAGE 745
36.6.2 Name: Network Configuration Register EMAC_NCFG Address: 0xFFFBC004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 IRXFCS 18 EFRHD 17 DRFCS 16 RLCE 14 13 PAE 12 RTY 11 10 9 – 8 BIG 5 NBC 4 CAF 3 JFRAME 2 – 1 FD 0 SPD 15 RBOF 7 UNI 6 MTI CLK • SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin.
PAGE 746
• CLK: MDC clock divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations) CLK MDC 00 MCK divided by 8 (MCK up to 20 MHz) 01 MCK divided by 16 (MCK up to 40 MHz) 10 MCK divided by 32 (MCK up to 80 MHz) 11 MCK divided by 64 (MCK up to 160 MHz) • RTY: Retry test Must be set to zero for normal operation.
PAGE 747
36.6.3 Name: Network Status Register EMAC_NSR Address: 0xFFFBC008 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – • MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. • IDLE 0 = The PHY logic is running. 1 = The PHY management logic is idle (i.e., has completed).
PAGE 748
36.6.4 Name: Transmit Status Register EMAC_TSR Address: 0xFFFBC014 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UND 5 COMP 4 BEX 3 TGO 2 RLE 1 COL 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
PAGE 749
36.6.5 Name: Receive Buffer Queue Pointer Register EMAC_RBQP Address: 0xFFFBC018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
PAGE 750
36.6.6 Name: Transmit Buffer Queue Pointer Register EMAC_TBQP Address: 0xFFFBC01C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
PAGE 751
36.6.7 Name: Receive Status Register EMAC_RSR Address: 0xFFFBC020 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 OVR 1 REC 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
PAGE 752
36.6.8 Name: Interrupt Status Register EMAC_ISR Address: 0xFFFBC024 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 WOL 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. • RCOMP: Receive Complete A frame has been stored in memory. Cleared on read.
PAGE 753
• PTZ: Pause Time Zero • Set when the pause time register, 0x38 decrements to zero. Cleared on a read.WOL: Wake On LAN Set when a WOL event has been triggered (This flag can be set even if the EMAC is not clocked). Cleared on a read.
PAGE 754
36.6.9 Name: Interrupt Enable Register EMAC_IER Address: 0xFFFBC028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 WOL 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Enable management done interrupt. • RCOMP: Receive Complete Enable receive complete interrupt. • RXUBR: Receive Used Bit Read Enable receive used bit read interrupt.
PAGE 755
• PTZ: Pause Time Zero Enable pause time zero interrupt. • WOL: Wake On LAN Enable Wake On LAN interrupt.
PAGE 756
36.6.10 Name: Interrupt Disable Register EMAC_IDR Address: 0xFFFBC02C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 WOL 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Disable management done interrupt. • RCOMP: Receive Complete Disable receive complete interrupt.
PAGE 757
• PTZ: Pause Time Zero Disable pause time zero interrupt. • WOL: Wake On LAN Disable Wake On LAN interrupt.
PAGE 758
36.6.11 Name: Interrupt Mask Register EMAC_IMR Address: 0xFFFBC030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 WOL 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Management done interrupt masked. • RCOMP: Receive Complete Receive complete interrupt masked. • RXUBR: Receive Used Bit Read Receive used bit read interrupt masked.
PAGE 759
• PTZ: Pause Time Zero Pause time zero interrupt masked. • WOL: Wake On LAN Wake On LAN interrupt masked.
PAGE 760
36.6.12 Name: PHY Maintenance Register EMAC_MAN Address: 0xFFFBC034 Access: Read-write 31 30 29 SOF 28 27 26 RW 23 PHYA 22 15 14 21 13 25 24 17 16 PHYA 20 REGA 19 18 CODE 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA • DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. • CODE: Must be written to 10. Reads as written.
PAGE 761
36.6.13 Name: Pause Time Register EMAC_PTR Address: 0xFFFBC038 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PTIME 7 6 5 4 PTIME • PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
PAGE 762
36.6.14 Name: Hash Register Bottom EMAC_HRB Address: 0xFFFBC090 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Bits 31:0 of the hash address register. See “Hash Addressing” on page 734. 36.6.
PAGE 763
36.6.16 Name: Specific Address 1 Bottom Register EMAC_SA1B Address: 0xFFFBC098 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 36.6.
PAGE 764
36.6.18 Name: Specific Address 2 Bottom Register EMAC_SA2B Address: 0xFFFBC0A0 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 36.6.
PAGE 765
36.6.20 Name: Specific Address 3 Bottom Register EMAC_SA3B Address: 0xFFFBC0A8 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 36.6.
PAGE 766
36.6.22 Name: Specific Address 4 Bottom Register EMAC_SA4B Address: 0xFFFBC0B0 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 36.6.
PAGE 767
36.6.24 Name: Type ID Checking Register EMAC_TID Address: 0xFFFBC0B8 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID • TID: Type ID checking For use in comparisons with received frames TypeID/Length field. 36.6.
PAGE 768
36.6.26 Name: Access: Wake-on-LAN Register EMAC_WOL Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 MTI 18 SA1 17 ARP 16 MAG 15 14 13 12 11 10 9 8 3 2 1 0 IP 7 6 5 4 IP • IP: ARP request IP address Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake-on-LAN event. A value of zero does not generate an event, even if this is matched by the received frame.
PAGE 769
36.6.27 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers. 36.6.27.
PAGE 770
36.6.27.3 Name: Single Collision Frames Register EMAC_SCF Address: 0xFFFBC044 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SCF 7 6 5 4 SCF • SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 36.6.27.
PAGE 771
36.6.27.5 Name: Frames Received OK Register EMAC_FRO Address: 0xFFFBC04C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 FROK 15 14 13 12 FROK 7 6 5 4 FROK • FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory.
PAGE 772
36.6.27.
PAGE 773
36.6.27.9 Name: Late Collisions Register EMAC_LCOL Address: 0xFFFBC05C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 LCOL • LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision. 36.6.27.
PAGE 774
36.6.27.11 Name: Transmit Underrun Errors Register EMAC_TUND Address: 0xFFFBC064 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TUND • TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented. 36.6.27.
PAGE 775
36.6.27.13 Name: Receive Resource Errors Register EMAC_RRE Address: 0xFFFBC06C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RRE 7 6 5 4 RRE • RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 36.6.27.
PAGE 776
36.6.27.15 Name: Receive Symbol Errors Register EMAC_RSE Address: 0xFFFBC074 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RSE • RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception.
PAGE 777
36.6.27.17 Name: Receive Jabbers Register EMAC_RJA Address: 0xFFFBC07C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RJB • RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. 36.6.
PAGE 778
36.6.27.19 Name: SQE Test Errors Register EMAC_STE Address: 0xFFFBC084 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SQER • SQER: SQE test errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 36.6.27.
PAGE 779
37. USB High Speed Host Port (UHPHS) 37.1 Description The USB High Speed Host Port (UHPHS) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as Enhanced HCI protocol (Enhanced Host Controller Interface). 37.2 Embedded Characteristics The SAM9M10 features USB communication ports as follows: • 2 Ports USB Host full speed OHCI and High speed EHCI • 1 Device High speed USB Host Port A is directly connected to the first UTMI transceiver.
PAGE 780
The USB Host Port controller is fully compliant with the Open HCI specification. The USB Host Port User Interface (registers description) can be found in the Open HCI Rev 1.0 Specification available on http://h18000.www1.hp.com/productinfo/development/openhci.html. The standard OHCI USB stack driver can be easily ported to Atmel’s architecture, in the same way all existing class drivers run without hardware specialization.
PAGE 781
37.3 Block Diagram Figure 37-2. Block Diagram HCI Slave Block AHB Slave OHCI Registers Root Hub Registers List Processor Block Control ED & TD Regsisters PORT S/M 1 Root Hub and Host SIE AHB Master HCI Master Block Data PORT S/M 0 FIFO 64 x 8 SOF generator HCI Slave Block AHB Slave EHCI Registers Embedded USB v2.
PAGE 782
37.4 Product Dependencies 37.4.1 I/O Lines HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High Speed physical transceivers are controlled by the USB host controller. 37.5 I/O Lines HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High Speed physical transceivers are controlled by the USB host controller. One transceiver is shared with USB Device (UDP) High Speed.
PAGE 783
Figure 37-3. UHP Clock trees UPLL (480 MHz) AHB EHCI Master Interface 30 MHz UTMI transceiver USB 2.0 EHCI Host Controller Port Router 30 MHz EHCI User Interface UTMI transceiver MCK OHCI Master Interface Root Hub and Host SIE UHP48M UHP12M OHCI User Interface USB 1.1 OHCI Host Controller OHCI clocks 37.5.2 Interrupt The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
PAGE 784
37.6 Typical Connection Figure 37-4. Board Schematic to Interface UHP High-speed Device Controller PIO (VBUS DETECT) 15k Ω (1) "A" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND HHSDM 39 ± 5% Ω HFSDM 3 4 (1) 22k Ω Shell = Shield HHSDP CRPB 1 2 39 ± 5% Ω CRPB: 1μF to 10μF HFSDP 6K8 ± 1% Ω VBG 10 pF GNDUTMI Note: 1. The values shown on the 22k Ω and 15k Ω resistors are only valid for 3v3 supplied PIOs.
PAGE 785
38. USB High Speed Device Port (UDPHS) 38.1 Description The USB High Speed Device Port (UDPHS) is compliant with the Universal Serial Bus (USB), rev 2.0 High Speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a dual-port RAM used to store the current data payload. If two or three banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
PAGE 786
Table 38-1. UDPHS Endpoint Description Mnemonic Nb Bank DMA High BandWidth Max. Endpoint Size Endpoint Type 0 EPT_0 1 N N 64 Control 1 EPT_1 2 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt 2 EPT_2 2 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt 3 EPT_3 3 Y N 1024 Ctrl/Bulk/Iso(1)/Interrupt 4 EPT_4 3 Y N 1024 Ctrl/Bulk/Iso(1)/Interrupt 5 EPT_5 3 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt 6 EPT_6 3 Y Y 1024 Ctrl/Bulk/Iso(1)/Interrupt Endpoint # Note: 1.
PAGE 787
38.3 Block Diagram Figure 38-2. Block Diagram APB Interface APB bus ctrl status DHSDP DHSDM AHB1 AHB bus Rd/Wr/Ready DMA AHB0 APB bus UTMI USB2.0 CORE DFSDP DP DFSDM DM Master AHB Multiplexeur Slave Local AHB Slave interface EPT Alloc 32 bits DPRAM System Clock Domain 16/8 bits USB Clock Domain PMC Notes: 1. System clock, bit (1 << AT91C_ID_UDPHS) in PMC_PCER register. 2. Enable UDPHS clock (peripheral clock) bit AT91C_CKGR_UPLLEN in PMC_UCKR register. 3.
PAGE 788
38.4 Typical Connection Figure 38-3. Board Schematic PIO (VBUS DETECT) 15k Ω (1) "B" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND 1 2 3 4 DHSDM 39 ± 5% Ω DFSDM Shell = Shield (1) 22k Ω CRPB DHSDP 39 ± 5% Ω CRPB:1μF to 10μF DFSDP 6K8 ± 1% Ω VBG 10 pF GNDUTMI Notes: 1. The values shown on the 22kΩ and 15kΩ resistors are only valid with 3V3 supplied PIOs.
PAGE 789
38.5 Functional Description 38.5.1 USB V2.0 High Speed Device Port Introduction The USB V2.0 High Speed Device Port provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB Device through a set of communication flows. 38.5.2 USB V2.
PAGE 790
Notes: 1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake. 2. Isochronous transfers must use endpoints configured with two or three banks. An endpoint handles all transactions related to the type of transfer for which it has been configured. 38.5.4 USB V2.0 High Speed BUS Transactions Each transfer results in one or more transactions over the USB bus. There are five kinds of transactions flowing across the bus in packets: 1. 2. 3. 4. 5.
PAGE 791
Control endpoints can generate interrupts and use only 1 bank. All endpoints (except endpoint 0) can be configured either as Bulk, Interrupt or Isochronous. See Table 38-1. UDPHS Endpoint Description. The maximum packet size they can accept corresponds to the maximum endpoint size. Note: The endpoint size of 1024 is reserved for isochronous endpoints. The size of the DPRAM is 4 KB. The DPR is shared by all active endpoints.
PAGE 792
Figure 38-5. Logical Address Space for DPR Access: DPR x banks Logical address 8 to 64 B 8 to 64 B 8 to 64 B 8 to 64 B ... 8 to1024 B 64 KB EP0 8 to1024 B 64 KB 8 to1024 B 8 to1024 B EP1 ... 64 KB EP2 y banks z banks 8 to1024 B 8 to1024 B 64 KB EP3 ... Configuration examples of UDPHS_EPTCTLx (UDPHS Endpoint Control Register) for Bulk IN endpoint type follow below. • With DMA – AUTO_VALID: Automatically validate the packet and switch to the next bank. – EPT_ENABL: Enable endpoint.
PAGE 793
38.5.6 Transfer With DMA USB packets of any length may be transferred when required by the UDPHS Device. These transfers always feature sequential addressing. Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance boost with paged memories.
PAGE 794
38.5.7 Transfer Without DMA Important. If the DMA is not to be used, it is necessary that it be disabled because otherwise it can be enabled by previous versions of software without warning. If this should occur, the DMA can process data before an interrupt without knowledge of the user.
PAGE 795
38.5.8.2 NYET NYET is a High Speed only handshake. It is returned by a High Speed endpoint as part of the PING protocol. High Speed devices must support an improved NAK mechanism for Bulk OUT and control endpoints (except setup stage). This mechanism allows the device to tell the host whether it has sufficient endpoint space for the next OUT transfer (see USB 2.0 spec 8.5.1 NAK Limiting via Ping Flow Control).
PAGE 796
The application is notified that it is possible to write a new packet to the DPR by the TX_PK_RDY interrupt. This interrupt can be enabled or masked by setting the TX_PK_RDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register. Algorithm Description to Fill Several Packets: Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application overhead by writing linearly several banks at the same time.
PAGE 797
may fetch a new transfer descriptor from the memory address pointed by the UDPHS_DMANXTDSCx register. Once the transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register. To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be stopped. To do so, INTDIS_DMA and TX_BK_RDY may be set in the UDPHS_EPTCTLENBx register. It is also possible for the application to wait for the completion of all transfers.
PAGE 798
Figure 38-9.
PAGE 799
Figure 38-11. Data OUT Followed by Status IN Transfer Host Sends the Last Data Payload to the Device USB Bus Packets Token OUT Data OUT Device Sends a Status IN to the Host ACK Token IN Data IN ACK Interrupt Pending RX_BK_RDY (UDPHS_EPTSTAx) Cleared by Firmware Set by Hardware TX_PK_RDY (UDPHS_EPTSTAx) Set by Firmware Clear by Hardware Note: Before proceeding to the status stage, the software should determine that there is no risk of extra data from the host (data stage).
PAGE 800
38.5.8.7 Isochronous IN Isochronous-IN is used to transmit a stream of data whose timing is implied by the delivery rate. Isochronous transfer provides periodic, continuous communication between host and device. It guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc. If the endpoint is not available (TX_PK_RDY = 0), then the device does not answer to the host. An ERR_FL_ISO interrupt is generated in the UDPHS_EPTSTAx register and once enabled, then sent to the CPU.
PAGE 801
• ERR_FLUSH + ERR_TRANS: The first token IN has been answered and it was the only one received, a second bank has been validated but not the third, whereas NB_TRANS was waiting for three transactions. • ERR_FL_ISO + ERR_FLUSH + ERR_TRANS: The first token IN has been treated, the data for the second Token IN was not available in time, but the second bank has been validated before the end of the microframe. The third bank has not been validated, but three transactions have been set in NB_TRANS. 38.5.8.
PAGE 802
– END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB packet has been transferred by the DMA, if the USB transfer ended with a short packet. (Beneficial when the receive size is unknown.) – CHANN_ENB: Run and stop at end of buffer. For OUT transfer, the bank will be automatically cleared by hardware when the application has read all the bytes in the bank (the bank is empty).
PAGE 803
Figure 38-14.
PAGE 804
– MData0/Data1/Data2 • If NB_TRANS = 2, the sequence should be either – MData0 – MData0/Data1 • If NB_TRANS = 1, the sequence should be – Data0 38.5.8.
PAGE 805
38.5.8.15 STALL STALL is returned by a function in response to an IN token or after the data phase of an OUT or in response to a PING transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request is not supported. • OUT To stall an endpoint, set the FRCESTALL bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has been set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register. • IN Set the FRCESTALL bit in UDPHS_EPTSETSTAx register.
PAGE 806
38.5.9 Speed Identification The high speed reset is managed by the hardware. At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. At the end of the reset process (full or high), the ENDRESET interrupt is generated. Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device. 38.5.10 USB V2.0 High Speed Global Interrupt Interrupts are defined in Section 38.6.
PAGE 807
Figure 38-18.
PAGE 808
38.5.12 Power Modes 38.5.12.1 Controlling Device States A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus Specification, Rev 2.0. Figure 38-19.
PAGE 809
38.5.12.2 Not Powered State Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a host, device power consumption can be reduced by the DETACH bit in UDPHS_CTRL. Disabling the transceiver is automatically done. HSDM, HSDP, FSDP and FSDP lines are tied to GND pull-downs integrated in the hub downstream ports. 38.5.12.
PAGE 810
In this state bus powered devices must drain less than 500 μA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The UDPHS device peripheral clocks can be switched off. Resume event is asynchronously detected. 38.5.12.
PAGE 811
38.5.13 Test Mode A device must support the TEST_MODE feature when in the Default, Address or Configured High Speed device states. TEST_MODE can be: • Test_J • Test_K • Test_Packet • Test_SEO_NAK (See Section 38.6.7 “UDPHS Test Register” on page 823 for definitions of each test mode.
PAGE 812
38.6 USB High Speed Device Port (UDPHS) User Interface Table 38-5.
PAGE 813
38.6.1 Name: UDPHS Control Register UDPHS_CTRL Address: 0xFFF78000 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 PULLD_DIS 10 REWAKEUP 9 DETACH 8 EN_UDPHS 7 FADDR_EN 6 5 4 3 DEV_ADDR 2 1 0 • DEV_ADDR: UDPHS Address Read: This field contains the default address (0) after power-up or UDPHS bus reset.
PAGE 814
• DETACH: Detach Command Read: 0 = UDPHS is attached. 1 = UDPHS is detached, UTMI transceiver is suspended. Write: 0 = pull up the DP line (attach command). 1 = simulate a detach on the UDPHS line and force the UTMI transceiver into suspend state (Suspend M = 0). (See PULLD_DIS description below.) • REWAKEUP: Send Remote Wake Up Read: 0 = Remote Wake Up is disabled. 1 = Remote Wake Up is enabled. Write: 0 = no effect. 1 = force an external interrupt on the UDPHS controller for Remote Wake UP purposes.
PAGE 815
38.6.2 Name: UDPHS Frame Number Register UDPHS_FNUM Address: 0xFFF78004 Access: Read 31 FNUM_ERR 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 FRAME_NUMBER 9 8 7 6 5 FRAME_NUMBER 4 3 1 MICRO_FRAME_NUM 0 2 • MICRO_FRAME_NUM: Microframe Number Number of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1 ms). One microframe is received each 125 microseconds (1 ms/8).
PAGE 816
38.6.3 Name: UDPHS Interrupt Enable Register UDPHS_IEN Address: 0xFFF78010 Access: Read-write 31 – 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Enable Read: 0 = Suspend Interrupt is disabled. 1 = Suspend Interrupt is enabled.
PAGE 817
• ENDRESET: End Of Reset Interrupt Enable Read: 0 = End Of Reset Interrupt is disabled. 1 = End Of Reset Interrupt is enabled. Write: 0 = disable End Of Reset Interrupt. 1 = enable End Of Reset Interrupt. Automatically enabled after USB reset. • WAKE_UP: Wake Up CPU Interrupt Enable Read: 0 = Wake Up CPU Interrupt is disabled. 1 = Wake Up CPU Interrupt is enabled. Write 0 = disable Wake Up CPU Interrupt. 1 = enable Wake Up CPU Interrupt.
PAGE 818
• DMA_x: DMA Channel x Interrupt Enable Read: 0 = the interrupts for this channel are disabled. 1 = the interrupts for this channel are enabled. Write: 0 = disable the interrupts for this channel. 1 = enable the interrupts for this channel.
PAGE 819
38.6.4 Name: UDPHS Interrupt Status Register UDPHS_INTSTA Address: 0xFFF78014 Access: Read-only 31 – 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 SPEED • SPEED: Speed Status 0 = reset by hardware when the hardware is in Full Speed mode.
PAGE 820
• WAKE_UP: Wake Up CPU Interrupt 0 = cleared by setting the WAKE_UP bit in UDPHS_CLRINT. 1 = set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation.
PAGE 821
38.6.5 Name: UDPHS Clear Interrupt Register UDPHS_CLRINT Address: 0xFFF78018 Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Clear 0 = no effect. 1 = clear the DET_SUSPD bit in UDPHS_INTSTA. • MICRO_SOF: Micro Start Of Frame Interrupt Clear 0 = no effect.
PAGE 822
38.6.6 Name: UDPHS Endpoints Reset Register UDPHS_EPTRST Address: 0xFFF7801C Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 EPT_6 5 EPT_5 4 EPT_4 3 EPT_3 2 EPT_2 1 EPT_1 0 EPT_0 • EPT_x: Endpoint x Reset 0 = no effect. 1 = reset the Endpointx state. Setting this bit clears the Endpoint status UDPHS_EPTSTAx register, except for the TOGGLESQ_STA field.
PAGE 823
38.6.
PAGE 824
• OPMODE2: OpMode2 Read and write: 0 = no effect. 1 = set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI encoding. Note: For the Test mode, Test_SE0_NAK (see Universal Serial Bus Specification, Revision 2.0: 7.1.20, Test Mode Support). Force the device in High Speed mode, and configure a bulk-type endpoint. Do not fill this endpoint for sending NAK to the host.
PAGE 825
38.6.
PAGE 826
38.6.
PAGE 827
38.6.
PAGE 828
• FIFO_MAX_SIZE: DPRAM Size 0 = if DPRAM is 128 bytes deep. 1 = if DPRAM is 256 bytes deep. 2 = if DPRAM is 512 bytes deep. 3 = if DPRAM is 1024 bytes deep. 4 = if DPRAM is 2048 bytes deep. 5 = if DPRAM is 4096 bytes deep. 6 = if DPRAM is 8192 bytes deep. 7 = if DPRAM is 16384 bytes deep. • BW_DPRAM: DPRAM Byte Write Capability 0 = if DPRAM Write Data Shadow logic is implemented. 1 = if DPRAM is byte write capable.
PAGE 829
38.6.11 Name: UDPHS Endpoint Configuration Register UDPHS_EPTCFGx [x=0..
PAGE 830
:Endpoint Type 00 Control endpoint 01 Isochronous endpoint 10 Bulk endpoint 11 Interrupt endpoint • BK_NUMBER: Number of Banks Read and write: Set this field according to the endpoint’s number of banks (see Section 38.5.5 ”Endpoint Configuration”).
PAGE 831
38.6.12 Name: UDPHS Endpoint Control Enable Register UDPHS_EPTCTLENBx [x=0..
PAGE 832
1 = enable Overflow Error Interrupt. • RX_BK_RDY: Received OUT Data Interrupt Enable 0 = no effect. 1 = enable Received OUT Data Interrupt. • TX_COMPLT: Transmitted IN Data Complete Interrupt Enable 0 = no effect. 1 = enable Transmitted IN Data Complete Interrupt. • TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable 0 = no effect. 1 = enable TX Packet Ready/Transaction Error Interrupt. • RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable 0 = no effect.
PAGE 833
38.6.13 Name: UDPHS Endpoint Control Disable Register UDPHS_EPTCTLDISx [x=0..
PAGE 834
• ERR_OVFLW: Overflow Error Interrupt Disable 0 = no effect. 1 = disable Overflow Error Interrupt. • RX_BK_RDY: Received OUT Data Interrupt Disable 0 = no effect. 1 = disable Received OUT Data Interrupt. • TX_COMPLT: Transmitted IN Data Complete Interrupt Disable 0 = no effect. 1 = disable Transmitted IN Data Complete Interrupt. • TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable 0 = no effect. 1 = disable TX Packet Ready/Transaction Error Interrupt.
PAGE 835
38.6.14 Name: UDPHS Endpoint Control Register UDPHS_EPTCTLx [x=0..
PAGE 836
If the exception raised is not associated to a new system bank packet (NAK_IN, NAK_OUT, ERR_FL_ISO...), then the request cancellation may happen at any time and may immediately stop the current DMA transfer. This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate.
PAGE 837
• STALL_SNT/ERR_CRISO/ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled 0 = Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 = Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. • NAK_IN/ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled 0 = NAKIN Interrupt is masked. 1 = NAKIN/Bank Flush Error Interrupt is enabled. • NAK_OUT: NAKOUT Interrupt Enabled 0 = NAKOUT Interrupt is masked. 1 = NAKOUT Interrupt is enabled.
PAGE 838
38.6.15 Name: UDPHS Endpoint Set Status Register UDPHS_EPTSETSTAx [x=0..6] Addresses: 0xFFF78114 [0], 0xFFF78134 [1], 0xFFF78154 [2], 0xFFF78174 [3], 0xFFF78194 [4], 0xFFF781B4 [5], 0xFFF781D4 [6] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 TX_PK_RDY 10 – 9 KILL_BANK 8 – 7 – 6 – 5 FRCESTALL 4 – 3 – 2 – 1 – 0 – • FRCESTALL: Stall Handshake Request Set 0 = no effect.
PAGE 839
38.6.16 Name: UDPHS Endpoint Clear Status Register UDPHS_EPTCLRSTAx [x=0..
PAGE 840
• NAK_IN/ERR_FLUSH: NAKIN/Bank Flush Error Clear 0 = no effect. 1 = clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. • NAK_OUT: NAKOUT Clear 0 = no effect. 1 = clear the NAK_OUT flag of UDPHS_EPTSTAx.
PAGE 841
38.6.17 Name: UDPHS Endpoint Status Register UDPHS_EPTSTAx [x=0..
PAGE 842
Note 4: This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable endpoint). • ERR_OVFLW: Overflow Error This bit is set by hardware when a new too-long packet is received. Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set. This bit is updated at the same time as the BYTE_COUNT field.
PAGE 843
If one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe, then this bit is still set as long as the current bank contains one “bad” n-transaction. (see “CURRENT_BANK/CONTROL_DIR: Current Bank/Control Direction” on page 844) As soon as the current bank is relative to a new “good” n-transactions, then this bit is reset. Note1: A transaction error occurs when the toggle sequencing does not respect the Universal Serial Bus Specification, Rev 2.0 (5.9.
PAGE 844
– ERR_FLUSH: (for High Bandwidth Isochronous IN endpoints) This bit is set when flushing unsent banks at the end of a microframe. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint). • NAK_OUT: NAK OUT This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
PAGE 845
This field is also updated at TX_PK_RDY flag set with the next bank. This field is reset by EPT_x of UDPHS_EPTRST register. • SHRT_PCKT: Short Packet An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
PAGE 846
38.6.18 UDPHS DMA Channel Transfer Descriptor The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer.
PAGE 847
38.6.19 Name: UDPHS DMA Next Descriptor Address Register UDPHS_DMANXTDSCx [x = 1..5] Addresses: 0xFFF78320 [1], 0xFFF78330 [2], 0xFFF78340 [3], 0xFFF78350 [4], 0xFFF78360 [5] Access: Read-write 31 30 29 28 27 NXT_DSC_ADD 26 25 24 23 22 21 20 19 NXT_DSC_ADD 18 17 16 15 14 13 12 11 NXT_DSC_ADD 10 9 8 7 6 5 4 3 NXT_DSC_ADD 2 1 0 • NXT_DSC_ADD This field points to the next channel descriptor to be processed.
PAGE 848
38.6.20 Name: UDPHS DMA Channel Address Register UDPHS_DMAADDRESSx [x = 1..5] Addresses: 0xFFF78324 [1], 0xFFF78334 [2], 0xFFF78344 [3], 0xFFF78354 [4], 0xFFF78364 [5] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUFF_ADD 23 22 21 20 BUFF_ADD 15 14 13 12 BUFF_ADD 7 6 5 4 BUFF_ADD • BUFF_ADD This field determines the AHB bus starting address of a DMA channel transfer. Channel start and end addresses may be aligned on any byte boundary.
PAGE 849
38.6.21 Name: UDPHS DMA Channel Control Register UDPHS_DMACONTROLx [x = 1..
PAGE 850
• END_TR_EN: End of Transfer Enable (Control) Used for OUT transfers only. 0 = USB end of transfer is ignored. 1 = UDPHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close the current buffer and the UDPHS_DMASTATUSx register END_TR_ST flag will be raised. This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure.
PAGE 851
38.6.22 Name: UDPHS DMA Channel Status Register UDPHS_DMASTATUSx [x = 1..
PAGE 852
• DESC_LDST: Descriptor Loaded Status 0 = cleared automatically when read by software. 1 = set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
PAGE 853
39. Image Sensor Interface (ISI) 39.1 Description The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller.
PAGE 854
Figure 39-1. ISI Connection Example Image Sensor Image Sensor Interface ISI_DATA[11..0] data[11..0] 39.
PAGE 855
39.4 Functional Description The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock.
PAGE 856
Figure 39-4. SAV and EAV Sequence Synchronization ISII_PCK DATA[7..0] 39.4.2 FF 00 00 SAV 80 Y Cb Y Cr Y Cb Y Cr Active Video Y Y Cr Y Cb FF 00 00 EAV 9D Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. All the sensors do not output the YCbCr or RGB components in the same order.
PAGE 857
Table 39-5.
PAGE 858
39.4.4 Preview Path 39.4.4.1 Scaling, Decimation (Subsampling) This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. Table 39-6. Decimation Factor Dec value 0->15 16 17 18 19 ... 124 125 126 127 Dec Factor X 1 1.063 1.
PAGE 859
Figure 39-5. Resize Examples 1280 32/16 decimation 640 1024 480 1280 56/16 decimation 352 1024 288 39.4.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: C0 0 C1 Y – Y off R G = C 0 – C 2 – C 3 × C b – C boff B C0 C4 0 C r – C roff Example of programmable value to convert YCrCb to RGB: ⎧ R = 1.
PAGE 860
39.4.4.3 Memory Interface Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:6:5 format compliant with 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue channels, and two LSBs from the green channel.
PAGE 861
Figure 39-6.
PAGE 862
39.4.5 Codec Path 39.4.5.1 Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below: Y Cr = C0 C1 C2 Cb –C 6 –C 7 C 8 C 3 –C 4 –C 5 Y off R × G + Cr off B Cb off An example of coefficients is given below: ⎧ Y = 0.257 ⋅ R + 0.504 ⋅ G + 0.098 ⋅ B + 16 ⎪ ⎨ C r = 0.439 ⋅ R – 0.368 ⋅ G – 0.
PAGE 863
39.5 Image Sensor Interface (ISI) User Interface Table 39-9.
PAGE 864
39.5.1 Name: ISI Configuration 1 Register ISI_CFG1 Access: Read-write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 SFD 23 22 21 20 SLD 15 – 14 7 CRC_SYNC 6 EMB_SYNC 13 12 FULL 11 DISCR 10 9 FRATE 8 5 – 4 PIXCLK_POL 3 VSYNC_POL 2 HSYNC_POL 1 – 0 – THMASK • HSYNC_POL: Horizontal Synchronization Polarity 0: HSYNC active high. 1: HSYNC active low. • VSYNC_POL: Vertical Synchronization Polarity 0: VSYNC active high. 1: VSYNC active low.
PAGE 865
• THMASK: Threshold Mask 0: Only 4 beats AHB burst are allowed. 1: Only 4 and 8 beats AHB burst are allowed. 2: 4, 8 and 16 beats AHB burst are allowed. • SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. • SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame.
PAGE 866
39.5.2 Name: ISI Configuration 2 Register ISI_CFG2 Access: Read-write Reset Value: 0x00000000 31 30 29 RGB_CFG 23 28 27 - 26 25 IM_HSIZE 24 20 19 18 17 16 YCC_SWAP 22 21 IM_HSIZE 15 COL_SPACE 14 RGB_SWAP 13 GRAYSCALE 12 RGB_MODE 11 GS_MODE 10 9 IM_VSIZE 8 7 6 5 4 3 2 1 0 IM_VSIZE • IM_VSIZE: Vertical Size of the Image Sensor [0..2047]: Vertical size = IM_VSIZE + 1. • GS_MODE: 0: 2 pixels per word. 1: 1 pixel per word. • RGB_MODE: RGB Input Mode: 0: RGB 8:8:8 24 bits.
PAGE 867
• YCC_SWAP: Defines the YCC Image Data YCC_SWAP Byte 0 Byte 1 Byte 2 Byte 3 00: Default Cb(i) Y(i) Cr(i) Y(i+1) 01: Mode1 Cr(i) Y(i) Cb(i) Y(i+1) 10: Mode2 Y(i) Cb(i) Y(i+1) Cr(i) 11: Mode3 Y(i) Cr(i) Y(i+1) Cb(i) • RGB_CFG: Defines RGB Pattern when RGB_MODE is set to 1 RGB_CFG Byte 0 Byte 1 Byte 2 Byte 3 00: Default R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B 01: Mode1 B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R 10: Mode2 G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB) 11: Mode3 G(LSB)/B
PAGE 868
39.5.3 Name: ISI Preview Register ISI_PSIZE Access: Read-write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 23 22 21 20 19 18 17 11 – 10 – 9 3 2 1 24 PREV_HSIZE 16 PREV_HSIZE 15 – 14 – 13 – 12 – 7 6 5 4 8 PREV_VSIZE 0 PREV_VSIZE • PREV_VSIZE: Vertical Size for the Preview Path Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode).
PAGE 869
39.5.4 Name: ISI Preview Decimation Factor Register ISI_PDECF Access: Read-write Reset Value: 0x00000010 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 DEC_FACTOR • DEC_FACTOR: Decimation Factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation.
PAGE 870
39.5.5 Name: ISI Color Space Conversion YCrCb to RGB Set 0 Register ISI_Y2R_SET0 Access: Read-write Reset Value: 0x6832cc95 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 C3 23 22 21 20 C2 15 14 13 12 C1 7 6 5 4 C0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/128, ranges from 0 to 1.9921875. • C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, ranges from 0 to 1.9921875.
PAGE 871
39.5.6 Name: ISI Color Space Conversion YCrCb to RGB Set 1 Register ISI_Y2R_SET1 Access: Read-write Reset Value: 0x00007102 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 Cboff 13 Croff 12 Yoff 11 – 10 – 9 – 8 C4 C4 • C4: Color Space Conversion Matrix Coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875. • Yoff: Color Space Conversion Luminance Default Offset 0: No offset. 1: Offset = 128.
PAGE 872
39.5.7 Name: ISI Color Space Conversion RGB to YCrCb Set 0 Register ISI_R2Y_SET0 Access: Read-write Reset Value: 0x01324145 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Roff 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 C2 15 14 13 12 C1 7 6 5 4 C0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375. • C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875.
PAGE 873
39.5.8 Name: ISI Color Space Conversion RGB to YCrCb Set 1 Register ISI_R2Y_SET1 Access: Read-write Reset Value: 0x01245e38 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 Goff 19 18 17 16 11 10 9 8 3 2 1 0 C5 15 14 13 12 C4 7 6 5 4 C3 • C3: Color Space Conversion Matrix Coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875. • C4: Color Space Conversion Matrix Coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375.
PAGE 874
39.5.9 Name: ISI Color Space Conversion RGB to YCrCb Set 2 Register ISI_R2Y_SET2 Access: Read-write Reset Value: 0x01384a4b 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Boff 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 C8 15 14 13 12 C7 7 6 5 4 C6 • C6: Color Space Conversion Matrix Coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875. • C7: Color Space Conversion Matrix Coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375.
PAGE 875
39.5.10 Name: ISI Control Register ISI_CTRL Access: Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 ISI_CDC 7 – 6 – 5 – 4 – 3 – 2 ISI_SRST 1 ISI_DIS 0 ISI_EN • ISI_EN: ISI Module Enable Request Write one to this field to enable the module. Software must poll ENABLE field in the ISI_STATUS register to verify that the command has successfully completed.
PAGE 876
39.5.11 Name: ISI Status Register ISI_SR Access: Read Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 SIP 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 CDC_PND 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 ENABLE • ENABLE (this bit is a status bit) 0: Module is enabled. 1: Module is disabled. • DIS_DONE: Module Disable Request has Terminated 1: Disable request has completed.
PAGE 877
1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. This flag is reset after a read operation. • C_OVR: Codec Datapath Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. This flag is reset after a read operation.
PAGE 878
39.5.
PAGE 879
39.5.
PAGE 880
39.5.14 Name: ISI Interrupt Mask Register ISI_IMR Access: Read-write Reset Value: 0x0 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 – 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 – • DIS_DONE: Module Disable Operation Completed 0: The disable completed interrupt is disabled. 1: The disable completed interrupt is enabled.
PAGE 881
• FR_OVR: Frame Rate Overrun 0: The frame overrun interrupt is disabled. 1: The frame overrun interrupt is enabled.
PAGE 882
39.5.15 Name: DMA Channel Enable Register DMA_CHER Access: Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_EN 0 P_CH_EN • P_CH_EN: Preview Channel Enable Write one to this field to enable the preview DMA channel. • C_CH_EN: Codec Channel Enable Write one to this field to enable the codec DMA channel.
PAGE 883
39.5.16 Name: DMA Channel Disable Register DMA_CHDR Access: Write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_DIS 0 P_CH_DIS • P_CH_DIS Write one to this field to disable the channel. Poll P_CH_S in DMA_CHSR to verify that the preview channel status has been successfully modified. • C_CH_DIS Write one to this field to disabled the channel.
PAGE 884
39.5.17 Name: DMA Channel Status Register DMA_CHSR Access: Read Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_S 0 P_CH_S • P_CH_S: 0: indicates that the Preview DMA channel is disabled 1: indicates that the Preview DMA channel is enabled. • C_CH_S: 0: indicates that the Codec DMA channel is disabled.
PAGE 885
39.5.18 Name: DMA Preview Base Address Register DMA_P_ADDR Access: Read-write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – P_ADDR 23 22 21 20 P_ADDR 15 14 13 12 P_ADDR 7 6 5 4 P_ADDR • P_ADDR: Preview Image Base Address. (This address is word aligned.
PAGE 886
39.5.19 Name: DMA Preview Control Register DMA_P_CTRL Access: Read-write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 P_DONE 2 P_IEN 1 P_WB 0 P_FETCH • P_FETCH: Descriptor Fetch Control Field 0: Preview channel fetch operation is disabled. 1: Preview channel fetch operation is enabled.
PAGE 887
39.5.20 Name: DMA Preview Descriptor Address Register DMA_P_DSCR Access: Read-write Reset Value: 31 0x00000000 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – P_DSCR 23 22 21 20 P_DSCR 15 14 13 12 P_DSCR 7 6 5 4 P_DSCR • P_DSCR: Preview Descriptor Base Address (This address is word aligned.
PAGE 888
39.5.21 Name: DMA Codec Base Address Register DMA_C_ADDR Access: Read-write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – C_ADDR 23 22 21 20 C_ADDR 15 14 13 12 C_ADDR 7 6 5 4 C_ADDR • C_ADDR: Codec Image Base Address (This address is word aligned.
PAGE 889
39.5.22 Name: DMA Codec Control Register DMA_C_CTRL Access: Read-write Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 C_DONE 2 C_IEN 1 C_WB 0 C_FETCH • C_FETCH: Descriptor Fetch Control Field 0: Codec channel fetch operation is disabled. 1: Codec channel fetch operation is enabled.
PAGE 890
39.5.23 Name: DMA Codec Descriptor Address Register DMA_C_DSCR Access: Read-write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – C_DSCR 23 22 21 20 C_DSCR 15 14 13 12 C_DSCR 7 6 5 4 C_DSCR • C_DSCR: Codec Descriptor Base Address (This address is word aligned.
PAGE 891
39.5.24 Name: ISI Write Protection Control ISI_WPCR Access: Read-write 31 30 29 28 27 WP_KEY (0x49 => “I”) 26 25 24 23 22 21 20 19 WP_KEY (0x53 => “S”) 18 17 16 15 14 13 12 11 WP_KEY (0x49 => “I”) 10 9 8 7 6 5 2 1 0 WP_EN 4 3 • WP_PEN: Write Protection Enable 0 = Disables the Write Protection if WP_KEY corresponds. 1 = Enables the Write Protection if WP_KEY corresponds. • WP_KEY: Write Protection KEY Password Should be written at value 0x495349 (ASCII code for “ISI”).
PAGE 892
39.5.25 Name: ISI Write Protection Status ISI_WPSR Access: Read-write 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 - 24 - 19 18 17 16 11 10 9 8 3 2 1 0 WP_VSRC 15 14 13 12 WP_VSRC 7 - 6 - 5 - 4 - WP_VS • WP_VSRC: Write Protection Violation Status WP_VS 0 0 0 0 No Write Protection Violation occurred since the last read of this register (WP_SR). 0 0 0 1 Write Protection detected unauthorized attempt to write a control register had occurred (since the last read).
PAGE 893
40. Touch Screen ADC Controller (TSADCC) 40.1 Description The Touch Screen ADC Controller is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC).
PAGE 894
40.3 Block Diagram Figure 40-1. TSADCC Block Diagram TSADC VDDANA TSADCC Memory Controller ADTRG PIO Trigger Selection Timer Touch Screen Sequencer ADC Control Logic PDC User Interface Peripheral Bridge APB Touch Screen Switches AD1XM AD2YP AD3YM Successive Approximation Register Analog-to-Digital Converter TSADC Clock PMC ....
PAGE 895
40.4 Signal Description Table 40-1. TSADCC Pin Description Pin Name Description VDDANA Analog power supply TSADVREF Reference voltage AD0XP Analog input channel 0 or Touch Screen Top channel AD1XM Analog input channel 1 or Touch Screen Bottom channel AD2YP Analog input channel 2 or Touch Screen Right channel AD3YM Analog input channel 3 or Touch Screen Left channel GPAD4 - GPAD7 General-purpose analog input channels 4 to 7 TSADTRG External trigger 40.5 Product Dependencies 40.5.
PAGE 896
40.6 Analog-to-digital Converter Functional Description The TSADCC embeds a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The ADC supports 8-bit or 10-bit resolutions. The conversion is performed on a full range between 0V and the reference voltage pin TSADVREF. Analog inputs between these voltages convert to values based on a linear conversion. 40.6.1 ADC Resolution The ADC supports 8-bit or 10-bit resolutions.
PAGE 897
40.6.5 Sample and Hold Time In the same way, a minimal Sample and Hold Time is necessary for the TSADCC to guarantee the best converted final value between selection of two channels. This time depends on the input impedance of the analog input, but also on the output impedance of the driver providing the signal to the analog input, as there is no input buffer amplifier.
PAGE 898
40.7.2 Position Measurement Method As shown in Figure 40-2, to detect the position of a contact, a supply is first applied from top to bottom. Due to the linear resistance of the film, there is a voltage gradient from top to bottom. When a contact is performed on the screen, the voltage propagates at the point the two surfaces come into contact with the second film.
PAGE 899
Figure 40-3. Touch Screen Switches Implementation XP VDDANA XM GND To the ADC YP VDDANA YM GND VDDANA VDDANA Switch Resistor Switch Resistor YP XP XP YP YM XM Switch Resistor Switch Resistor GND Horizontal Position Detection 40.7.3 GND Vertical Position Detection Pressure Measurement Method The method to measure the pressure (Rp) applied to the touch screen is based on the knowledge of the X-Panel resistance (Rxp).
PAGE 900
VDDANA VDDANA Switch Resistor Switch Resistor XP YP YP Open circuit Switch Resistor XP YP Rp YM XM GND XPos Measure(Yp) Rp YM XM YM XM Open circuit Switch Resistor Switch Resistor Open circuit XP Rp 40.7.4 VDDANA Switch Resistor GND GND Z1 Measure(Xp) Z2 Measure(Xp) Pen Detect Method When there is no contact, it is not necessary to perform conversion. However, it is important to detect a contact by keeping the power consumption as low as possible.
PAGE 901
Figure 40-4. Touch Screen Pen Detect XP XM YP YM VDDANA GND To the ADC VDDANA GND PENDBC Debouncer Pen Interrupt GND The Touch Screen Pen Detect can be used to generate a TSADCC interrupt to wake up the system or it can be programmed to trig a conversion, so that a position can be measured as soon as a contact is detected if the TSADCC is programmed for an operating mode involving the Touch Screen.
PAGE 902
40.8 Conversion Results When a conversion is completed, the resulting 8-bit or 10-bit digital value is right-aligned and stored in the “TSADCC Channel Data Register x (x = 0..7)” of the current channel and in the “TSADCC Last Converted Data Register”. The channel EOC bit and the bit DRDY in the “TSADCC Status Register” are both set. If the PDC channel is enabled, DRDY rising triggers a data transfer. In any case, either EOC and DRDY can trigger an interrupt.
PAGE 903
Figure 40-6.
PAGE 904
40.9 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the “TSADCC Control Register” with the bit START at 1.
PAGE 905
40.10.2 Touch Screen Mode Writing TSAMOD to “Touch Screen Only Mode” automatically enables the touch screen pins as analog inputs, and thus disables the digital function of the corresponding pins. In Touch Screen Mode, the channels 0 to 3 corresponding to the Touch Screen inputs are automatically activated and the bits CH0 to CH3 are automatically set in the “TSADCC Channel Status Register”.
PAGE 906
3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. Convert Channel Xp and store the result in both TSADCC_Z1DR and TSADCC_LCDR. Close the switches on the inputs XM and YP during the Sample and Hold Time. Convert Channel YM and store the result in both TSADCC_Z2DR and TSADCC_LCDR. Close the switches on the inputs XP and XM during the Sample and Hold Time. Convert Channel XM and store the result in TSADCC_CDR1. Close the switches on the inputs XP and XM during the Sample and Hold Time.
PAGE 907
In the Interleaved Mode, the channels 0 to 3 corresponding to the Touch Screen inputs are automatically activated and the bits CH0 to CH3 are automatically set in the “TSADCC Channel Status Register”. This mode allows periodic conversion of the remaining channels at high sampling rate and converted data transferred in memory with the PDC while the touch screen conversions are performed at low rate.
PAGE 908
3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corresponding TSADCC_CDRx and TSADCC_LCDR. 4. Set Trigger Counter to 4. • For Trigger Counter at 4: 1. Close the switches on the inputs YP and YM during the Sample and Hold Time. 2. Convert Channel YP, subtract TSADCC_CDR3 from the result and store the subtraction result in TSADCC_CDR2 (and also in TSADCC_LCDR if PDCEN is enabled). 3.
PAGE 909
1. Close the switches on the inputs XP and XM during the Sample and Hold Time. 2. Convert Channel XM and store the result in TSADCC_CDR1. 3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corresponding TSADCC_CDRx and TSADCC_LCDR. 4. Set Trigger Counter to 3. • For Trigger Counter at 3: 1. Close the switches on the inputs XP and XM during the Sample and Hold Time. 2.
PAGE 910
• For Trigger Counter between 8 and (2TSFREQ+1): 1. Increment Trigger Counter. 2. If Trigger Counter equals (2TSFREQ+1), then set Trigger Counter to 0. 3. If Channel 4 to Channel 7 are enabled, convert Channels and store result in the corresponding TSADCC_CDRx and TSADCC_LCDR. The Trigger Counter is cleared when TSAMOD is written to define the Interleaved Mode, then it simply rolls over. 40.10.4 Manual Mode The TSADCC features a manual mode allowing to control the state (open/close) of the four switches.
PAGE 911
40.11 Touch Screen ADC Controller (TSADCC) User Interface Table 40-4.
PAGE 912
40.11.1 Name: TSADCC Control Register TSADCC_CR Address: 0xFFFB0000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – START SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the TSADCC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion.
PAGE 913
40.11.
PAGE 914
• PENDET: Pen Detect Selection 0: Disable the Touch screen pins as analog inputs 1: enable the Touch screen pins as analog inputs • PRES: Pressure Measurement Selection 0: Disable the pressure measurement function 1: enable the pressure measurement function • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8/ADCCLK • SHTIM: Sample & Hold Time for ADC Channels Programming 0 for SHTIM gives a Sample & Hold Time equal to 1/ADCCLK.
PAGE 915
40.11.
PAGE 916
40.11.4 Name: TSADCC Touch Screen Register TSADCC_TSR Address: 0xFFFB000C Access: Read/Write 31 30 29 28 – – – – 25 24 23 22 21 20 19 – – – – – 18 17 16 – – – 15 14 13 12 11 10 9 8 – – – – – – – – 3 2 1 0 7 6 5 4 – – – – 27 26 TSSHTIM TSFREQ • TSFREQ: Touch Screen Frequency in Interleaved Mode Effective only if the Touch Screen Interleaved Mode is selected. Defines the Touch Screen Frequency compared to the Trigger Frequency.
PAGE 917
40.11.5 Name: TSADCC Channel Enable Register TSADCC_CHER Address: 0xFFFB0010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel.
PAGE 918
40.11.6 Name: TSADCC Channel Disable Register TSADCC_CHDR Address: 0xFFFB0014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel.
PAGE 919
40.11.7 Name: TSADCC Channel Status Register TSADCC_CHSR Address: 0xFFFB0018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
PAGE 920
40.11.
PAGE 921
• EOCXp: End of Conversion X Position 0 = The pressure measurement is disabled or the Xp conversion is not finished. 1 = The pressure measurement is enabled and the Xp conversion is complete • EOCZ1: End of Conversion Z1 Measure 0 = The pressure measurement is disabled or the Z1 conversion is not finished. 1 = The pressure measurement is enabled and the Z1 conversion is complete • EOCZ2: End of Conversion Z2 Measure 0 = The pressure measurement is disabled or the Z2 conversion is not finished.
PAGE 922
40.11.9 Name: TSADCC Channel Data Register x (x = 0..7) TSADCC_CDR0..
PAGE 923
40.11.
PAGE 924
40.11.
PAGE 925
40.11.
PAGE 926
40.11.14 TSADCC X Position Data Register Name: TSADCC_XPDR. Address: 0xFFFB0050 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – 7 6 5 4 8 DATA – – 3 2 1 0 DATA • DATA: X Position Data 40.11.15 TSADCC Z1 Data Register Name: TSADCC_Z1DR.
PAGE 927
40.11.16 TSADCC Z2 Data Register Name: TSADCC_Z2DR. Address: 0xFFFB0058 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – 7 6 5 4 8 Z2 – – 3 2 1 0 Z2 • DATA: Z2 Measurement Data 40.11.17 TSADCC Manual Switch Command Register Name: TSADCC_MSCR.
PAGE 928
40.11.18 TSADCC Write Protection Mode Register Name: TSADCC_WPMR Address: 0xFFFB00E4 Access: Read-Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN 26 25 24 18 17 16 10 9 8 • WPEN: Write Protection of TSADCC_MR, TSADCC_TRGR and TSADCC_TSR 0 and KEY= 0x545341 Write protection is disabled. 1 and KEY = 0x545341, Write Protection is enabled. 40.11.
PAGE 929
41. DMA Controller (DMAC) 41.1 Description The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer.
PAGE 930
– DMA chaining support for multiple non-contiguous data blocks through use of linked lists – Scatter support for placing fields into a system memory area from a contiguous transfer.
PAGE 931
41.3 Block Diagram Figure 41-1.
PAGE 932
41.4 Functional Description 41.4.1 Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
PAGE 933
Figure 41-2. DMAC Transfer Hierarchy for Non-Memory Peripheral HDMA Transfer Buffer Buffer Chunk Transfer AMBA Burst Transfer DMA Transfer Level Buffer Transfer Level Buffer Chunk Transfer Chunk Transfer AMBA Single Transfer AMBA Burst Transfer AMBA Burst Transfer Single Transfer DMA Transaction Level AMBA Single Transfer AMBA Transfer Level Figure 41-3.
PAGE 934
Single-buffer DMAC transfer: Consists of a single buffer. Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. The source and destination can independently select which method to use. – Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory where the next linked list item (LLI) exists.
PAGE 935
41.4.2 Memory Peripherals Figure 41-3 on page 933 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled.
PAGE 936
41.4.4 DMAC Transfer Types A DMAC transfer may consist of single or multi-buffers transfers.
PAGE 937
Figure 41-5.
PAGE 938
41.4.4.3 Table 41-2.
PAGE 939
41.4.4.6 Suspension of Transfers Between buffers At the end of every buffer transfer, an end of buffer interrupt is asserted if: • the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the channel number. Note: The buffer complete interrupt is generated at the completion of the buffer transfer to the destination. At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if: • the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.
PAGE 940
41.4.5 Programming a Channel Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used. The different transfer types are shown in Table 41-2 on page 938. The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are enabled.
PAGE 941
f. If source picture-in-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x. g. If destination picture-in-picture mode is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx register for channel x. 4. After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n is the channel number. Make sure that bit 0 of DMAC_EN.ENABLE register is enabled. 5.
PAGE 942
8. If source picture-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x. 9. If destination picture-in-picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx register for channel x. 10. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the status register: DMAC_EBCISR. 11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in Table 41-2 on page 938. 12.
PAGE 943
Figure 41-6. Multi-buffer with Linked List Address for Source and Destination Address of Destination Layer Address of Source Layer Buffer 2 SADDR(2) Buffer 2 DADDR(2) Buffer 1 SADDR(1) Buffer 1 DADDR(1) Buffer 0 Buffer 0 DADDR(0) SADDR(0) Source Buffers Destination Buffers If the user needs to execute a DMAC transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx.
PAGE 944
The DMAC transfer flow is shown in Figure 41-8 on page 944. Figure 41-8. DMAC Transfer Flow for Source and Destination Linked List Address Channel enabled by software LLI Fetch Hardware reprograms SADDRx, DADDRx, CTRLA/Bx, DSCRx DMAC buffer transfer Writeback of HDMA_CTRLAx register in system memory Buffer Complete interrupt generated here Is HDMA in Row1 of HDMA State Machine Table HDMA Transfer Complete interrupt generated here no yes Channel Disabled by hardware 41.4.5.
PAGE 945
a. Write the starting source address in the DMAC_SADDRx register for channel x. b. Write the starting destination address in the DMAC_DADDRx register for channel x. c. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 10 as shown in Table 41-2 on page 938. Program the DMAC_DSCRx register with ‘0’. d. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx register for channel x. For example, in the register, you can program the following: – i.
PAGE 946
in the DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit in the DMAC_CTRLBx.AUTO bit. This put the DMAC into Row 1 as shown in Table 412 on page 938. If the next buffer is not the last buffer in the DMAC transfer, then the reload bits should remain enabled to keep the DMAC in Row 4. b. If the buffer complete interrupt is masked (DMAC_EBCIMR.
PAGE 947
Figure 41-10. DMAC Transfer Flow for Source and Destination Address Auto-reloaded Channel Enabled by software Buffer Transfer Replay mode for SADDRx, DADDRx, CTRLAx, CTRLBx Buffer Complete interrupt generated here HDMA Transfer Complete Interrupt generated here yes Is HDMA in Row1 of HDMA State Machine table Channel Disabled by hardware no no EBCIMR[x]=1 yes Stall until STALLED is cleared by writing to KEEPON field 41.4.5.
PAGE 948
4. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel.
PAGE 949
interrupts, or poll for the Channel Enable (DMAC_CHSR.ENABLE) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 41-2 on page 938, the following step is performed. 19. The DMAC fetches the next LLI from memory location pointed to by the current DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers.
PAGE 950
Figure 41-12. DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address Channel Enabled by software LLI Fetch Hardware reprograms DADDRx, CTRLAx, CTRLBx, DSCRx DMA buffer transfer Writeback of control status information in LLI Reload SADDRx Buffer Complete interrupt generated here yes HDMA Transfer Complete interrupt generated here Is HDMA in Row1 of HDMA State Machine Table Channel Disabled by hardware 41.4.5.
PAGE 951
– Source AHB master interface layer in the SIF field where source resides. – Destination AHB master interface master layer in the DIF field where destination resides. – Incrementing/decrementing or fixed address for source in SRC_INCR field. – Incrementing/decrementing or fixed address for destination in DST_INCR field. e. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. f. If destination picture-in-picture is enabled (DMAC_CTRLBx.
PAGE 952
Figure 41-13.
PAGE 953
Figure 41-14. DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address Channel Enabled by software Buffer Transfer Replay mode for SADDRx, Contiguous mode for DADDRx CTRLAx, CTRLBx Buffer Complete interrupt generated here Buffer Transfer Complete interrupt generated here yes Is HDMA in Row1of HDMA State Machine Table Channel Disabled by hardware no no DMA_EBCIMR[x]=1 yes Stall until STALLED field is cleared by software writing KEEPON Field 41.4.5.
PAGE 954
Note: The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. 4. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively.
PAGE 955
DMAC_DADDRx register is left unchanged. The DMAC transfer continues until the DMAC samples the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that described in Row 1 of Table 41-2 on page 938. The DMAC then knows that the previous buffer transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 41-15 on page 955 Note that the destination address is decrementing. Figure 41-15.
PAGE 956
Figure 41-16.
PAGE 957
41.4.6 Disabling a Channel Prior to Transfer Completion Under normal operation, software enables a channel by writing a ‘1’ to the Channel Handler Enable Register, DMAC_CHER.ENABLE[n], and hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENABLE[n] register bit. The recommended way for software to disable a channel without losing data is to use the SUSPEND[n] bit in conjunction with the EMPTY[n] bit in the Channel Handler Status Register. 1.
PAGE 958
41.5 DMAC Software Requirements • There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel. • When destination peripheral is defined as the flow controller, source single transfer request are not serviced until Destination Peripheral has asserted its Last Transfer Flag.
PAGE 959
41.6 DMA Controller (DMAC) User Interface Table 41-3.
PAGE 960
41.6.1 Name: DMAC Global Configuration Register DMAC_GCFG Address: 0xFFFFEC00 Access: Read-write Reset: 0x00000010 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ARB_CFG 3 – 2 – 1 – 0 – Note: Bit fields 0, 1, 2, 3, have a default value of 0. This should not be changed. • ARB_CFG 0: Fixed priority arbiter. 1: Modified round robin arbiter.
PAGE 961
41.6.2 Name: DMAC Enable Register DMAC_EN Address: 0xFFFFEC04 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 ENABLE • ENABLE 0: DMA Controller is disabled. 1: DMA Controller is enabled. 41.6.
PAGE 962
41.6.4 Name: DMAC Software Chunk Transfer Request Register DMAC_CREQ Address: 0xFFFFEC0C Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DCREQ7 14 SCREQ7 13 DCREQ6 12 SCREQ6 11 DCREQ5 10 SCREQ5 9 DCREQ4 8 SCREQ4 7 DCREQ3 6 SCREQ3 5 DCREQ2 4 SCREQ2 3 DCREQ1 2 SCREQ1 1 DCREQ0 0 SCREQ0 • DCREQx Request a destination chunk transfer on channel i. • SCREQx Request a source chunk transfer on channel i.
PAGE 963
41.6.
PAGE 964
41.6.6 Name: DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register DMAC_EBCIER Address: 0xFFFFEC18 Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTC[7:0] Buffer Transfer Completed Interrupt Enable Register.
PAGE 965
41.6.7 Name: DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register DMAC_EBCIDR Address: 0xFFFFEC1C Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTC[7:0] Buffer transfer completed Disable Interrupt Register.
PAGE 966
41.6.8 Name: DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register DMAC_EBCIMR Address: 0xFFFFEC20 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTC[7:0] 0: Buffer Transfer completed interrupt is disabled for channel i.
PAGE 967
41.6.9 Name: DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register DMAC_EBCISR Address: 0xFFFFEC24 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 ERR7 22 ERR6 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 CBTC7 14 CBTC6 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 BTC7 6 BTC6 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTC[7:0] When BTC[i] is set, Channel i buffer transfer has terminated.
PAGE 968
41.6.10 Name: DMAC Channel Handler Enable Register DMAC_CHER Address: 0xFFFFEC28 Access: Write-only Reset: 0x00000000 31 KEEP7 30 KEEP6 29 KEEP5 28 KEEP4 27 KEEP3 26 KEEP2 25 KEEP1 24 KEEP0 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SUSP7 14 SUSP6 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 ENA7 6 ENA6 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 • ENA[7:0] When set, a bit of the ENA field enables the relevant channel.
PAGE 969
41.6.11 Name: DMAC Channel Handler Disable Register DMAC_CHDR Address: 0xFFFFEC2C Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RES7 14 RES6 13 RES5 12 RES4 11 RES3 10 RES2 9 RES1 8 RES0 7 DIS7 6 DIS6 5 DIS5 4 DIS4 3 DIS3 2 DIS2 1 DIS1 0 DIS0 • DIS[7:0] Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is terminated.
PAGE 970
41.6.
PAGE 971
41.6.13 Name: DMAC Channel x [x = 0..7] Source Address Register DMAC_SADDRx [x = 0..7] Addresses: 0xFFFFEC3C [0], 0xFFFFEC64 [1], 0xFFFFEC8C [2], 0xFFFFECB4 [3], 0xFFFFECDC [4], 0xFFFFED04 [5], 0xFFFFED2C [6], 0xFFFFED54 [7] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SADDRx 23 22 21 20 SADDRx 15 14 13 12 SADDRx 7 6 5 4 SADDRx • SADDRx Channel x source address. This register must be aligned with the source transfer width.
PAGE 972
41.6.15 Name: DMAC Channel x [x = 0..7] Descriptor Address Register DMAC_DSCRx [x = 0..7] Addresses: 0xFFFFEC44 [0], 0xFFFFEC6C [1], 0xFFFFEC94 [2], 0xFFFFECBC [3], 0xFFFFECE4 [4], 0xFFFFED0[5] 0xFFFFED34 [6], 0xFFFFED5C [7] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 DSCRx 23 22 21 20 DSCRx 15 14 13 12 DSCRx 7 6 5 4 DSCRx 0 DSCRx_IF • DSCRx_IF 00: The Buffer Transfer descriptor is fetched via AHB-Lite Interface 0.
PAGE 973
41.6.16 Name: DMAC Channel x [x = 0..7] Control A Register DMAC_CTRLAx [x = 0..7] Addresses: 0xFFFFEC48 [0], 0xFFFFEC70 [1], 0xFFFFEC98 [2], 0xFFFFECC0 [3], 0xFFFFECE8 [4], 0xFFFFED10 [5], 0xFFFFED38 [6], 0xFFFFED60 [7] Access: Read-write Reset: 0x00000000 31 DONE 30 – 29 28 23 – 22 21 DCSIZE 20 15 14 13 12 DST_WIDTH 27 – 26 – 25 24 19 – 18 17 SCSIZE 16 11 10 9 8 3 2 1 0 SRC_WIDTH BTSIZE 7 6 5 4 BTSIZE • BTSIZE Buffer Transfer Size.
PAGE 974
DCSIZE Number of data transferred 100 32 101 64 110 128 111 256 • SRC_WIDTH SRC_WIDTH Single Transfer Size 00 BYTE 01 HALF-WORD 1X WORD • DST_WIDTH DST_WIDTH Single Transfer Size 00 BYTE 01 HALF-WORD 1X WORD • DONE 0: The transfer is performed. 1: If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the content of this register. The DONE field is written back to memory at the end of the transfer.
PAGE 975
41.6.17 Name: DMAC Channel x [x = 0..7] Control B Register DMAC_CTRLBx [x = 0..
PAGE 976
• DST_DSCR 0: Destination address is updated when the descriptor is fetched from the memory. 1: Buffer Descriptor Fetch operation is disabled for the destination. • FC This field defines which device controls the size of the buffer transfer, also referred as to the Flow Controller.
PAGE 977
41.6.18 Name: DMAC Channel x [x = 0..7] Configuration Register DMAC_CFGx [x = 0..
PAGE 978
• LOCK_IF 0: Interface Lock capability is disabled 1: Interface Lock capability is enabled • LOCK_B 0: AHB Bus Locking capability is disabled. 1: AHB Bus Locking capability is enabled. • LOCK_IF_L 0: The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1: The Master Interface Arbiter is locked by the channel x for a buffer transfer. • AHB_PROT AHB_PROT field provides additional information about a bus access and is primarily used to implement some level of protection.
PAGE 979
41.6.19 Name: DMAC Channel x [x = 0..7] Source Picture in Picture Configuration Register DMAC_SPIPx [x = 0..
PAGE 980
41.6.20 Name: DMAC Channel x [x = 0..7] Destination Picture in Picture Configuration Register DMAC_DPIPx [x = 0..
PAGE 981
42. Pulse Width Modulation Controller (PWM) 42.1 Description The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
PAGE 982
42.3 Block Diagram Figure 42-1. Pulse Width Modulation Controller Block Diagram PWM Controller PWMx Period Channel PWMx Update Duty Cycle Clock Selector Comparator PWMx Counter PIO PWM0 Channel Period PWM0 Update Duty Cycle Clock Selector PMC MCK Clock Generator Comparator PWM0 Counter APB Interface AIC Interrupt Generator APB 42.4 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 42-1.
PAGE 983
42.5 Product Dependencies 42.5.1 I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs.
PAGE 984
42.6.1 PWM Clock Generator Figure 42-2. Functional View of the Clock Generator Block Diagram MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A PREA clkA DIVA PWM_MR Divider B PREB clkB DIVB PWM_MR Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC).
PAGE 985
42.6.2 PWM Channel 42.6.2.1 Block Diagram Figure 42-3. Functional View of the Channel Block Diagram inputs from clock generator Channel Clock Selector Internal Counter Comparator PWMx output waveform inputs from APB bus Each of the 4 channels is composed of three blocks: • A clock selector which selects one of the clocks provided by the clock generator described in Section 42.6.1 “PWM Clock Generator” on page 984. • An internal counter clocked by the output of the clock selector.
PAGE 986
• By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( 2* X *CPRD*DIVA ) ( 2* X *CPRD*DIVB ) ----------------------------------------------------- or ----------------------------------------------------MCK MCK • the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
PAGE 987
Figure 42-5.
PAGE 988
42.6.3 PWM Controller Operations 42.6.3.1 Initialization Before enabling the output channel, this channel must have been configured by the software application: • Configuration of the clock generator if DIVA and DIVB are required • Selection of the clock for each channel (CPRE field in the PWM_CMRx register) • Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) • Configuration of the period for each channel (CPRD in the PWM_CPRDx register).
PAGE 989
Figure 42-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level.
PAGE 990
42.6.3.4 Interrupts Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.
PAGE 991
42.7 Pulse Width Modulation Controller (PWM) User Interface Table 42-4.
PAGE 992
42.7.1 Name: PWM Mode Register PWM_MR Address: 0xFFFB8000 Access: Read/Write 31 – 30 – 29 – 28 – 27 26 23 22 21 20 19 18 11 10 25 24 17 16 9 8 1 0 PREB DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB CLKA, CLKB 0 CLKA, CLKB clock is turned off 1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
PAGE 993
42.7.2 Name: PWM Enable Register PWM_ENA Address: 0xFFFB8004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. 42.7.
PAGE 994
42.7.4 Name: PWM Status Register PWM_SR Address: 0xFFFB800C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled. 42.7.
PAGE 995
42.7.6 Name: PWM Interrupt Disable Register PWM_IDR Address: 0xFFFB8014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x. 42.7.
PAGE 996
42.7.8 Name: PWM Interrupt Status Register PWM_ISR Address: 0xFFFB801C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
PAGE 997
42.7.9 Name: PWM Channel Mode Register PWM_CMR[0..
PAGE 998
42.7.10 Name: PWM Channel Duty Cycle Register PWM_CDTY[0..3] Addresses: 0xFFFB8204 [0], 0xFFFB8224 [1], 0xFFFB8244 [2], 0xFFFB8264 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
PAGE 999
42.7.11 Name: PWM Channel Period Register PWM_CPRD[0..3] Addresses: 0xFFFB8208 [0], 0xFFFB8228 [1], 0xFFFB8248 [2], 0xFFFB8268 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 16 bits (internal channel counter size) are significant.
PAGE 1000
42.7.12 Name: PWM Channel Counter Register PWM_CCNT[0..3] Addresses: 0xFFFB820C [0], 0xFFFB822C [1], 0xFFFB824C [2], 0xFFFB826C [3] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register).
PAGE 1001
42.7.13 Name: PWM Channel Update Register PWM_CUPD[0..3] Addresses: 0xFFFB8210 [0], 0xFFFB8230 [1], 0xFFFB8250 [2], 0xFFFB8270 [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.
PAGE 1002
SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 1002
PAGE 1003
43. AC97 Controller (AC97C) 43.1 Description The AC97 Controller is the hardware implementation of the AC97 digital controller (DC’97) compliant with AC97 Component Specification 2.2. The AC97 Controller communicates with an audio codec (AC97) or a modem codec (MC’97) via the AC-link digital serial interface. All digital audio, modem and handset data streams, as well as control (command/status) informations are transferred in accordance to the AC-link protocol.
PAGE 1004
43.3 Block Diagram Figure 43-1. Functional Block Diagram MCK Clock Domain Slot Number SYNC AC97 Slot Controller Slot Number 16/20 bits Slot #0 Transmit Shift Register M AC97 Tag Controller Receive Shift Register Slot #0,1 U AC97 CODEC Channel AC97C_COTHR AC97C_CORHR SDATA_OUT X Slot #1,2 Slot #2 Transmit Shift Register Receive Shift Register SDATA_IN AC97 Channel A Transmit Shift Register AC97C_CATHR AC97C_CARHR Slot #3...
PAGE 1005
43.4 Pin Name List Table 43-1. I/O Lines Description Pin Name Pin Description Type AC97CK 12.288-MHz bit-rate clock Input AC97RX Receiver Data (Referred as SDATA_IN in AC-link spec) Input AC97FS 48-KHz frame indicator and synchronizer Output AC97TX Transmitter Data (Referred as SDATA_OUT in AC-link spec) Output The AC97 reset signal provided to the primary codec can be generated by a PIO. 43.5 Application Block Diagram Figure 43-2.
PAGE 1006
43.6 Product Dependencies 43.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the AC97 Controller receiver, the PIO controller must be configured in order for the AC97C receiver I/O lines to be in AC97 Controller peripheral mode. Before using the AC97 Controller transmitter, the PIO controller must be configured in order for the AC97C transmitter I/O lines to be in AC97 Controller peripheral mode. Table 43-2. 43.6.
PAGE 1007
43.7 Functional Description 43.7.1 Protocol overview AC-link protocol is a bidirectional, fixed clock rate, serial digital stream. AC-link handles multiple input and output Pulse Code Modulation PCM audio streams, as well as control register accesses employing a Time Division Multiplexed (TDM) scheme that divides each audio frame in 12 outgoing and 12 incoming 20-bit wide data slots. Figure 43-3.
PAGE 1008
43.7.2 Slot Description 43.7.2.1 Tag Slot The tag slot, or slot 0, is a 16-bit wide slot that always goes at the beginning of an outgoing or incoming frame. Within tag slot, the first bit is a global bit that flags the entire frame validity. The next 12 bit positions sampled by the AC97 Controller indicate which of the corresponding 12 time slots contain valid data. The slot’s last two bits (combined) called Codec ID, are used to distinguish primary and secondary codec.
PAGE 1009
43.7.3 AC97 Controller Channel Organization The AC97 Controller features a Codec channel and 2 logical channels: Channel A, Channel B. The Codec channel controls AC97 Codec registers, it enables write and read configuration values in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot 1 and slot 2 exclusively, in both input and output directions. Channel A, Channel B transfer data to/from AC97 codec. All audio samples and modem data must transit by these 2 channels.
PAGE 1010
43.7.3.1 AC97 Controller Setup The following operations must be performed in order to bring the AC97 Controller into an operating state: 1. Enable the AC97 Controller clock in the PMC controller. 2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register (AC97C_MR). 3. Configure the input channel assignment by controlling the AC97 Controller Input Assignment Register (AC97C_ICA). 4.
PAGE 1011
In most cases, the AC97 Controller is embedded in chips that target audio player devices. In such cases, the AC97 Controller is exposed to heavy audio transfers. Using the polling technique increases processor overhead and may fail to keep the required pace under an operating system. In order to avoid these polling drawbacks, the application can perform audio streams by using PDC connected to channel A, which reduces processor overhead and increases performance especially under an operating system.
PAGE 1012
43.7.3.5 AC97 Input Frame The AC97 Controller receives a thirteen slot frame on the AC-Link sent by the AC97 Codec. The first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. Slots 1 and 2 are used if the application requires status informations from AC97 Codec. Slots [3:12] are used according to AC97 Controller Output Channel Assignment Register (AC97C_ICA) content.
PAGE 1013
43.7.3.10 To Transmit a10-bit Sample Stored in Big Endian Format on AC-link Halfword to be written in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR). 31 24 23 16 – 15 – 8 7 Byte0[7:0] 0 {0x00, Byte1[1:0]} Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit). 31 24 23 16 – 15 – 10 – 9 8 Byte1 [1:0] 7 0 Byte0[7:0] Data emitted on related slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}. 43.7.3.
PAGE 1014
43.7.4 Variable Sample Rate The problem of variable sample rate can be summarized by a simple example. When passing a 44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. The new AC97 standard approach calls for the addition of “on-demand” slot request flags.
PAGE 1015
The AC97 Codec can drive AC97RX signal from low to high level and holding it high until the controller issues either a cold or a worm reset. The AC97RX rising edge is asynchronously (regarding AC97FS) detected by the AC97 Controller. If WKUP bit is enabled in AC97C_IMR register, an interrupt is triggered that wakes up the AC97 Controller which should then immediately issue a cold or a warm reset.
PAGE 1016
43.8 AC97 Controller (AC97C) User Interface Table 43-6.
PAGE 1017
43.8.1 Name: AC97 Controller Mode Register AC97C_MR Address: 0xFFFAC008 Access: Read-Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 VRA 25 – 17 – 9 – 1 WRST 24 – 16 – 8 – 0 ENA • VRA: Variable Rate (for Data Slots 3-12) 0: Variable Rate is inactive. (48 KHz only) 1: Variable Rate is active. • WRST: Warm Reset 0: Warm Reset is inactive. 1: Warm Reset is active. • ENA: AC97 Controller Global Enable 0: No effect.
PAGE 1018
43.8.2 Name: AC97 Controller Input Channel Assignment Register AC97C_ICA Address: 0xFFFAC010 Access: Read-write 31 – 23 30 – 22 CHID10 14 15 CHID8 7 6 29 21 13 CHID7 5 CHID5 • CHIDx: Channel ID CHIDx 28 CHID12 20 12 4 CHID4 27 26 19 CHID9 11 18 3 25 CHID11 17 24 16 CHID8 10 CHID6 2 9 1 CHID3 8 CHID5 0 for the input slot x Selected Receive Channel 0x0 None. No data will be received during this slot time 0x1 Channel A data will be received during this slot time.
PAGE 1019
43.8.3 Name: AC97 Controller Output Channel Assignment Register AC97C_OCA Address: 0xFFFAC014 Access: Read-write 31 – 23 30 – 22 CHID10 14 15 CHID8 7 6 29 21 13 CHID7 5 CHID5 • CHIDx: Channel ID CHIDx 28 CHID12 20 12 4 CHID4 27 26 19 CHID9 11 18 3 25 CHID11 17 24 16 CHID8 10 CHID6 2 9 1 CHID3 8 CHID5 0 for the output slot x Selected Transmit Channel 0x0 None. No data will be transmitted during this slot time 0x1 Channel A data will be transferred during this slot time.
PAGE 1020
43.8.4 Name: AC97 Controller Codec Channel Receive Holding Register AC97C_CORHR Address: 0xFFFAC040 Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 SDATA SDATA • SDATA: Status Data Data sent by the CODEC in the third AC97 input frame slot (Slot 2).
PAGE 1021
43.8.5 Name: AC97 Controller Codec Channel Transmit Holding Register AC97C_COTHR Address: 0xFFFAC044 Access: Write-only 31 – 23 READ 15 30 – 22 29 – 21 28 – 20 14 13 12 27 – 19 CADDR 11 26 – 18 25 – 17 24 – 16 10 9 8 3 2 1 0 CDATA 7 6 5 4 CDATA • READ: Read-write command 0: Write operation to the CODEC register indexed by the CADDR address. 1: Read operation to the CODEC register indexed by the CADDR address.
PAGE 1022
43.8.6 Name: AC97 Controller Channel A, Channel B, Receive Holding Register AC97C_CARHR, AC97C_CBRHR Address: 0xFFFAC020 Address: 0xFFFAC030 Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDATA RDATA RDATA • RDATA: Receive Data Received Data on channel x. 43.8.
PAGE 1023
43.8.8 Name: AC97 Controller Channel A Status Register AC97C_CASR Address: 0xFFFAC028 Access: Read-only 31 – 23 – 15 RXBUFF 7 – 30 – 22 – 14 ENDRX 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 TXBUFE 3 – 26 – 18 – 10 ENDTX 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty.
PAGE 1024
• TXBUFE: Transmit Buffer Empty for Channel A 0: AC97C_CATCR or AC97C_CATNCR have a value other than 0. 1: Both AC97C_CATCR and AC97C_CATNCR have a value of 0. • ENDRX: End of Reception for Channel A 0: The register AC97C_CARCR has not reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR. 1: The register AC97C_CARCR has reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR. • RXBUFF: Receive Buffer Full for Channel A 0: AC97C_CARCR or AC97C_CARNCR have a value other than 0.
PAGE 1025
43.8.9 Name: AC97 Controller Channel B Status Register AC97C_CBSR Address: 0xFFFAC038 Access: Read-only 31 – 23 – 15 RXBUFF 7 – 30 – 22 – 14 ENDRX 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 – 3 – 26 – 18 – 10 TXBUFE 2 UNRUN 25 – 17 – 9 ENDTX 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty.
PAGE 1026
• TXBUFE: Transmit Buffer Empty for Channel B 0: AC97C_CBTCR or AC97C_CBTNCR have a value other than 0. 1: Both AC97C_CBTCR and AC97C_CBTNCR have a value of 0. • ENDRX: End of Reception for Channel B 0: The register AC97C_CBRCR has not reached 0 since the last write in AC97C_CBRCR or AC97C_CBRNCR. 1: The register AC97C_CBRCR has reached 0 since the last write in AC97C_CBRCR or AC97C_CBRNCR. • RXBUFF: Receive Buffer Full for Channel B 0: AC97C_CBRCR or AC97C_CBRNCR have a value other than 0.
PAGE 1027
43.8.10 Name: Address: AC97 Controller Codec Status Register AC97C_COSR 0xFFFAC048 Access: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty.
PAGE 1028
43.8.
PAGE 1029
• CEM: Channel A Endian Mode 0: Transferring Data through Channel A is straight forward (Little-Endian). 1: Transferring Data through Channel A from/to a memory is performed with from/to Big-Endian format translation. • CEN: Channel A Enable 0: Data transfer is disabled on Channel A. 1: Data transfer is enabled on Channel A. • PDCEN: Peripheral Data Controller Channel Enable 0: Channel A is not transferred through a Peripheral Data Controller Channel. Related PDC flags are ignored or not generated.
PAGE 1030
43.8.
PAGE 1031
• CEM: Channel B Endian Mode 0: Transferring Data through Channel B is straight forward (Little-Endian). 1: Transferring Data through Channel B from/to a memory is performed with from/to Big-Endian format translation. • CEN: Channel B Enable 0: Data transfer is disabled on Channel B. 1: Data transfer is enabled on Channel B. • PDCEN: Peripheral Data Controller Channel Enable 0: Channel B is not transferred through a Peripheral Data Controller Channel. Related PDC flags are ignored or not generated.
PAGE 1032
43.8.
PAGE 1033
43.8.14 Name: AC97 Controller Status Register AC97C_SR Address: 0xFFFAC050 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 CBEVT 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF WKUP and SOF flags in AC97C_SR register are automatically cleared by a processor read operation. • SOF: Start Of Frame 0: No Start of Frame has been detected since the last read of the Status Register.
PAGE 1034
43.8.15 Name: AC97 Codec Controller Interrupt Enable Register AC97C_IER Address: 0xFFFAC054 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 CBEVT 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event • CBEVT: Channel B Event 0: No Effect. 1: Enables the corresponding interrupt.
PAGE 1035
43.8.16 Name: AC97 Controller Interrupt Disable Register AC97C_IDR Address: 0xFFFAC058 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 CBEVT 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event • CBEVT: Channel B Event 0: No Effect. 1: Disables the corresponding interrupt.
PAGE 1036
43.8.17 Name: AC97 Controller Interrupt Mask Register AC97C_IMR Address: 0xFFFAC05C Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 CBEVT 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event • CBEVT: Channel B Event 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1037
44. True Random Number Generator (TRNG) 44.1 Description The True Random Number Generator (TRNG) passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. As soon as the TRNG is enabled (TRNG_CTRL register), the generator provides one 32-bit value every 84 clock cycles. Interrupt trng_int can be enabled through the TRNG_IER register (respectively disabled in TRNG_IDR).
PAGE 1038
44.2 True Random Number Generator (TRNG) User Interface Table 44-1.
PAGE 1039
44.2.1 Name: TRNG Control Register TRNG_CR Address: 0xFFFCC000 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – ENABLE • ENABLE: Enables the TRNG to provide random values 0 = Disables the TRNG. 1 = Enables the TRNG. • KEY: Security Key KEY = 0x524e47 (RNG in ASCII) This key is to be written when the ENABLE bit is set or cleared.
PAGE 1040
44.2.2 Name: TRNG Interrupt Enable Register TRNG_IER Address: 0xFFFCC010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
PAGE 1041
44.2.3 Name: TRNG Interrupt Disable Register TRNG_IDR Address: 0xFFFCC014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
PAGE 1042
44.2.4 Name: TRNG Interrupt Mask Register TRNG_IMR Address: 0xFFFCC018 Reset: 0x0000 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
PAGE 1043
44.2.5 Name: TRNG Interrupt Status Register TRNG_ISR Address: 0xFFFCC01C Reset: 0x0000 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0 = Output data is not valid or TRNG is disabled. 1 = New Random value is completed. DATRDY is cleared when this register is read.
PAGE 1044
44.2.6 Name: TRNG Output Data Register TRNG_ODATA Address: 0xFFFCC050 Reset: 0x0000 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data The 32-bit Output Data register contains the 32-bit random data.
PAGE 1045
45. LCD Controller (LCDC) 45.1 Description The LCD Controller (LCDC) consists of logic for transferring LCD image data from an external display buffer to an LCD module with integrated common and segment drivers. The LCD Controller supports single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a timebased dithering algorithm and Frame Rate Control (FRC) method.
PAGE 1046
45.3 Block Diagram Figure 45-1.
PAGE 1047
45.4 I/O Lines Description Table 45-1.
PAGE 1048
Table 45-2.
PAGE 1049
45.6 Functional Description The LCD Controller consists of two main blocks (Figure 45-1 on page 1046), the DMA controller and the LCD controller core (LCDC core). The DMA controller reads the display data from an external memory through a AHB master interface. The LCD controller core formats the display data. The LCD controller core continuously pumps the pixel data into the LCD module via the LCD data bus (LCDD[23:0]); this bus is timed by the LCDDOTCK, LCDDEN, LCDHSYNC, and LCDVSYNC signals. 45.6.
PAGE 1050
45.6.1.4 Channel-L This block has the same functionality as Channel-U, but for the Lower Panel in dual scan mode only. 45.6.1.5 Control This block receives the request signals from the LCDC core and generates the requests for the channels. 45.6.2 LCD Controller Core 45.6.2.1 Configuration Block The configuration block is a set of programmable registers that are used to configure the LCDC core operation. These registers are written via the AHB slave interface. Only word access is allowed.
PAGE 1051
• The input interface connects the datapath with the DMA controller. It is a dual FIFO interface with a data bus and two push lines that are used by the DMA controller to fill the FIFOs. • The output interface is a 24-bit data bus. The configuration of this interface depends on the type of LCD used (TFT or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface). • The configuration interface connects the datapath with the configuration block.
PAGE 1052
ister. It also adapts the memory-ordering format. Both big-endian and little-endian formats are supported. They are configured in the MEMOR field of the LCDCON2 register. The organization of the pixel data in the memory depends on the configuration and is shown in Table 45-5 and Table 45-7. Note: For a color depth of 24 bits per pixel there are two different formats supported: packed and unpacked.
PAGE 1053
Table 45-7. Big Endian Memory Organization (Continued) Mem Addr 0x3 0x2 Pixel 24bpp packed 0x1 0x0 1 Pixel 24bpp packed 2 2 3 Pixel 24bpp packed 4 Pixel 24bpp unpacked 5 not used Table 45-8.
PAGE 1054
45.6.2.5 Palette This block is used to generate the pixel gray or color information in palletized configurations. The different modes with the palletized/non-palletized configuration can be found in Table 45-9. In these modes, 1, 2, 4 or 8 input bits index an entry in the lookup table. The corresponding entry in the lookup table contains the color or gray shade information for the pixel. Table 45-9.
PAGE 1055
Table 45-11 shows the correspondences between the gray levels and the duty cycle. Table 45-11. Dithering Duty Cycle Gray Level Duty Cycle Pattern Register 15 1 - 14 6/7 DP6_7 13 4/5 DP4_5 12 3/4 DP3_4 11 5/7 DP5_7 10 2/3 DP2_3 9 3/5 DP3_5 8 4/7 DP4_7 7 1/2 ~DP1_2 6 3/7 ~DP4_7 5 2/5 ~DP3_5 4 1/3 ~DP2_3 3 1/4 ~DP3_4 2 1/5 ~DP4_5 1 1/7 ~DP6_7 0 0 - The duty cycles for gray levels 0 and 15 are 0 and 1, respectively.
PAGE 1056
Table 45-12. Dithering Algorithm for Monochrome Mode (Continued) Frame Number Pattern Pixel a Pixel b Pixel c Pixel d N+6 0101 OFF ON OFF ON N+7 1010 ON OFF ON OFF ... ... ... ... ... ... Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1. A color pixel is composed of three components: {R, G, B}. Pixel p0 will be displayed sending the color components {R0, G0, B0} to the display.
PAGE 1057
45.6.2.7 Shifter The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome mode and three sub-pixels at a time in color mode (R,G,B components). This module packs the data according to the output interface. This interface can be programmed in the DISTYPE, SCANMOD, and IFWIDTH fields of the LDCCON3 register. The DISTYPE field selects between TFT, STN monochrome and STN color display.
PAGE 1058
minimum period of the LCDDOTCK signal depends on the configuration. This information can be found in Table 45-14. f LCDC_clock f LCDDOTCK = ------------------------------CLKVAL + 1 The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the LCDCON2 register: • Always Active (used with TFT LCD Modules) • Active only when data is available (used with STN LCD Modules) Table 45-14.
PAGE 1059
45.6.2.9 Equation 1 ( VHDLY + HPW + HBP + 3 ) × PCLK_PERIOD ≥ DPATH_LATENCY where: • VHDLY, HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers • PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles • DPATH_LATENCY is the datapath latency of the configuration, given in Table 45-4 on page 1051 The LCDVSYNC is asserted once per frame. This signal is asserted to cause the LCD's line pointer to start over at the top of the display.
PAGE 1060
Figure 45-5. STN Panel Timing, CLKMOD 0 Frame Period LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD Line Period VHDLY+ HPW+1 HOZVAL+1 HBP+1 HFP+VHDLY+2 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1/2 PCLK 1/2 PCLK 1 PCLK Figure 45-6.
PAGE 1061
Figure 45-7. TFT Panel Timing (Line Expanded View), CLKMOD = 1 Line Period VHDLY+1 HPW+1 HOZVAL+1 HBP+1 HFP+VHDLY+2 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK 1/2 PCLK 1/2 PCLK Usually the LCD_FRM rate is about 70 Hz to 75 Hz.
PAGE 1062
The line counting is controlled by the read-only field LINECNT of LCDCON1 register. The LINECNT field decreases by one unit at each falling edge of LCDHSYNC. 45.6.2.10 Display This block is used to configure the polarity of the data and control signals. The polarity of all clock signals can be configured by LCDCON2[12:8] register setting. This block also generates the lcd_pwr signal internally used to control the state of the LCD pins and to turn on and off by software the LCD module.
PAGE 1063
connected to the upper panel data lines and the bus LCDD[15:8] is connected to the lower panel data lines. The rest of the LCD Data Bus lines (LCDD[23:16]) are not used. STN Mono displays require one bit of image data per pixel. STN Color displays require three bits (Red, Green and Blue) of image data per pixel, resulting in a horizontal shift register of length three times the number of pixels per horizontal line.
PAGE 1064
Figure 45-10.
PAGE 1065
Figure 45-11.
PAGE 1066
Figure 45-12.
PAGE 1067
Table 45-15.
PAGE 1068
45.7 Interrupts The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal LCD Core Clock. The IRQs are: • DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB slave while it is doing a data transfer. • FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when the FIFO is empty. • FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO while the FIFO is full.
PAGE 1069
– LCDFIFO register: To program it, use the formula in section “FIFO” on page 1051 – LCDMVAL register: Its configuration depends on the LCD Module used and should be tuned to improve the image quality in the display (See “Timegen” on page 1057.) – DP1_2 to DP6_7 registers: they are only used for STN displays. They contain the dithering patterns used to generate gray shades or colors in these modules. They are loaded with recommended patterns at reset, so it is not necessary to write anything on them.
PAGE 1070
45.10 2D Memory Addressing The LCDC can be configured to work on a frame buffer larger than the actual screen size. By changing the values in a few registers, it is easy to move the displayed area along the frame buffer width and height. Figure 45-13.
PAGE 1071
45.11 Register Configuration Guide Program the PIO Controller to enable LCD signals. Enable the LCD controller clock in the Power Management Controller. 45.11.1 STN Mode Example STN color(R,G,B) 320*240, 8-bit single scan, 70 frames/sec, Master clock = 60 Mhz Data rate: 320*240*70*3/8 = 2.016 MHz HOZVAL= ((3*320)/8) - 1 LINEVAL= 240 -1 CLKVAL = (60 MHz/2.
PAGE 1072
45.12 LCD Controller (LCDC) User Interface Table 45-16.
PAGE 1073
Table 45-16.
PAGE 1074
45.12.1 DMA Base Address Register 1 Name: DMABADDR1 Address:0x00500000 Access: Read-write Reset value: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 0 0 BADDR-U BADDR-U 15 14 13 12 7 6 5 4 BADDR-U BADDR-U • BADDR-U Base Address for the upper panel in dual scan mode. Base Address for the complete frame in single scan mode.
PAGE 1075
45.12.2 DMA Base Address Register 2 Name: DMABADDR2 Address:0x00500004 Access: Read-write Reset value: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BADDR-L BADDR-L 15 14 13 12 7 6 5 4 BADDR-L BADDR-L • BADDR-L Base Address for the lower panel in dual scan mode only.
PAGE 1076
45.12.3 DMA Frame Pointer Register 1 Name: DMAFRMPT1 Address:0x00500008 Access: Read-only Reset value: 0x00000000 31 – 23 – 15 30 – 22 29 – 21 14 13 7 6 5 28 – 20 27 – 19 FRMPT-U 12 11 FRMPT-U 4 3 FRMPT-U 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • FRMPT-U Current value of frame pointer for the upper panel in dual scan mode. Current value of frame pointer for the complete frame in single scan mode. Down count from FRMSIZE to 0.
PAGE 1077
45.12.5 DMA Frame Address Register 1 Name: DMAFRMADD1 Address:0x00500010 Access: Read-only Reset value: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FRMADD-U FRMADD-U 15 14 13 12 7 6 5 4 FRMADD-U FRMADD-U • FRMADD-U Current value of frame address for the upper panel in dual scan mode. Current value of frame address for the complete frame in single scan.
PAGE 1078
45.12.7 DMA Frame Configuration Register Name: DMAFRMCFG Address:0x00500018 Access: Read-write Reset value: 0x00000000 31 – 23 – 15 30 29 22 21 14 13 7 6 5 28 27 BRSTLN 20 19 FRMSIZE 12 11 FRMSIZE 4 3 FRMSIZE 26 25 24 18 17 16 10 9 8 2 1 0 • FRMSIZE: Frame Size In single scan mode, this is the frame size in words. In dual scan mode, this is the size of each panel.
PAGE 1079
45.12.8 DMA Control Register Name: DMACON Address:0x0050001C Access: Read-write Reset value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 DMA2DEN 27 – 19 – 11 – 3 DMAUPDT 26 – 18 – 10 – 2 DMABUSY 25 – 17 – 9 – 1 DMARST 24 – 16 – 8 – 0 DMAEN • DMAEN: DMA Enable 0: DMA is disabled. 1: DMA is enabled. • DMARST: DMA Reset (Write-only) 0: No effect. 1: Reset DMA module. DMA Module should be reset only when disabled and in idle state.
PAGE 1080
45.12.9 LCD DMA 2D Addressing Register Name: DMA2DCFG Address:0x00500020 Access: Read-write Reset value: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 27 25 24 19 – 11 26 PIXELOFF 18 – 10 20 – 12 17 – 9 16 – 8 7 6 5 4 3 2 1 0 ADDRINC ADDRINC • ADDRINC: DMA 2D Addressing Address increment When 2-D DMA addressing is enabled (bit DMA2DEN is set in register DMACON), this field specifies the number of bytes that the DMA controller must jump between screen lines.
PAGE 1081
45.12.10 LCD Control Register 1 Name: LCDCON1 Address:0x00500800 Access: Read-write, except LINECNT: Read-only Reset value: 0x00002000 31 30 29 28 27 26 25 24 21 20 19 17 16 13 12 5 – 4 – 11 – 3 – 18 CLKVAL 10 – 2 – 9 – 1 – 8 – 0 BYPASS LINECNT 23 15 7 – 22 LINECNT 14 CLKVAL 6 – • BYPASS: Bypass LCDDOTCK Divider 0: The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field. 1: The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency.
PAGE 1082
45.12.
PAGE 1083
• PIXELSIZE: Bits per pixel PIXELSIZE 0 0 0 1 bit per pixel 0 0 1 2 bits per pixel 0 1 0 4 bits per pixel 0 1 1 8 bits per pixel 1 0 0 16 bits per pixel 1 0 1 24 bits per pixel, packed (Only valid in TFT mode) 1 1 0 24 bits per pixel, unpacked (Only valid in TFT mode) 1 1 1 Reserved • INVVD: LCDD polarity 0: Normal 1: Inverted • INVFRAME: LCDVSYNC polarity 0: Normal (active high) 1: Inverted (active low) • INVLINE: LCDHSYNC polarity 0: Normal (active high) 1: Inverted (active
PAGE 1084
45.12.12 LCD Timing Configuration Register 1 Name: LCDTIM1 Address:0x00500808 Access: Read-write Reset value: 0x0000000 31 1 23 – 15 30 – 22 – 14 29 – 21 28 – 20 13 12 7 6 5 4 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VHDLY VPW VBP VFP • VFP: Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0.
PAGE 1085
45.12.13 LCD Timing Configuration Register 2 Name: LCDTIM2 Address:0x0050080C Access: Read-write Reset value: 0x0000000 31 30 29 28 27 26 25 24 23 22 HFP 14 – 6 21 13 20 – 12 19 – 11 18 – 10 17 – 9 16 – 8 5 4 3 2 1 0 HFP 15 – 7 HPW HBP • HBP: Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is (HBP+1) LCDDOTCK cycles. • HPW: Horizontal synchronization pulse width Width of the LCDHSYNC pulse, given in LCDDOTCK cycles.
PAGE 1086
45.12.
PAGE 1087
45.12.15 LCD FIFO Register Name: LCDFIFO Address:0x00500814 Access: Read-write Reset value: 0x0000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 FIFOTH FIFOTH • FIFOTH: FIFO Threshold Must be programmed with: FIFOTH (in Words) = 512 - (2 x DMA_BURST_LENGTH + 3) where: • 512 is the effective size of the FIFO in Words. It is the total FIFO memory size in single scan mode and half that size in dual scan mode.
PAGE 1088
45.12.16 LCDMOD Toggle Rate Value Register Name: LCDMVAL Access: Read-write Reset value: 0x00000000 31 MMODE 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 MVAL • MVAL: LCDMOD toggle rate value LCDMOD toggle rate if MMODE = 1. Toggle rate is MVAL + 1 line periods.
PAGE 1089
45.12.17 Dithering Pattern DP1_2 Register Name: DP1_2 Address:0x0050081C Access: Read-write Reset value: 0xA5 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 27 26 25 – 17 – 9 – 1 24 – 16 – 8 – 0 25 24 DP1_2 • DP1_2: Pattern value for ½ duty cycle 45.12.
PAGE 1090
45.12.19 Dithering Pattern DP3_5 Register Name: DP3_5 Address:0x00500824 Access: Read-write Reset value: 0xA5A5F 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 DP3_5 DP3_5 DP3_5 • DP3_5: Pattern value for 3/5 duty cycle 45.12.
PAGE 1091
45.12.21 Dithering Pattern DP5_7 Register Name: DP5_7: Address:0x0050082C Access: Read-write Reset value: 0xFAF5FA5 31 – 23 30 – 22 29 – 21 28 – 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 DP5_7 DP5_7 15 14 13 12 7 6 5 4 DP5_7 DP5_7 • DP5_7: Pattern value for 5/7 duty cycle 45.12.
PAGE 1092
45.12.23 Dithering Pattern DP4_5 Register Name: DP4_5 Address:0x00500834 Access: Read-write Reset value: 0xFAF5F 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 27 26 25 24 DP4_5 DP4_5 DP4_5 • DP4_5: Pattern value for 4/5 duty cycle 45.12.
PAGE 1093
45.12.25 Power Control Register Name: PWRCON Address:0x0050083C Access: Read-write Reset value: 0x0000000e 31 LCD_BUSY 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 GUARD_TIME 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 LCD_PWR • LCD_PWR: LCD module power control 0 = lcd_pwr signal is low, other lcd_* signals are low. 0->1 = lcd_* signals activated, lcd_pwr is set high with the delay of GUARD_TIME frame periods.
PAGE 1094
45.12.26 Contrast Control Register Name: CONTRAST_CTR Address:0x00500840 Access: Read-write Reset value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 ENA 26 – 18 – 10 – 2 POL 25 – 17 – 9 – 1 24 – 16 – 8 – 0 PS • PS This 2-bit value selects the configuration of a counter prescaler. The meaning of each combination is as follows: PS 0 0 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK.
PAGE 1095
45.12.27 Contrast Value Register Name: CONSTRAST_VAL Access: Read-write Reset value: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 CVAL • CVAL PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display.
PAGE 1096
45.12.
PAGE 1097
45.12.
PAGE 1098
45.12.
PAGE 1099
45.12.
PAGE 1100
45.12.
PAGE 1101
45.12.
PAGE 1102
45.12.
PAGE 1103
45.12.35 LCD Write Protect Mode Register Name: LCD_WPMR Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 — 6 — 5 — 4 — • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to0x4C4344 ("LCD" in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to0x4C4344 ("LCD" in ASCII).
PAGE 1104
45.12.36 LCD Write Protect Status Register Name: LCD_WPSR Address: 0x005008E8 Access: Read-only 31 — 30 — 29 — 28 — 23 22 21 20 27 — 26 — 25 — 24 — 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 — 6 — 5 — 4 — • WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the LCD_WPSR register. 1 = A Write Protect Violation occurred since the last read of the LCD_WPSR register.
PAGE 1105
46. Video Decoder (VDEC) 46.1 Description This document describes the features, functionality and system requirements of the multi-format decoder and covers all the issues that need to be considered when the decoder is being integrated in a particular software environment. A prior introduction to the H.264, MPEG-4/H.263, MPEG-2, MPEG-1, JPEG and VC-1 standards will also help understanding the functionality of the decoder. 46.2 Embedded Characteristics • Little-endian and Big-endian support.
PAGE 1106
46.3 Block Diagram Figure 46-1. Block Diagram Decoder Control Software Application Programming Interface MPEG-2 Strm. Header Decode MPEG-4/H.263 Strm. Header Decode H.264 Strm.
PAGE 1107
46.3.1 Decoding Features 46.3.1.1 H.264 Features Table 46-1. H.264 Features Feature Decoder Support Input data format H.264 byte or NAL unit stream Output data format YCbCr 4:2:0 semi-planar Supported image size 48 x 48 to 1280 x 720 Step size 16 pixels Maximum frame rate 30 fps at 720*576 (1) Maximum bit rate 57.2 Mbps Error detection and concealment Supported Note: 46.3.1.2 1. Actual maximum frame rate is given for logic clock frequency and system bus frequency at 133 MHz.
PAGE 1108
46.3.1.4 JPEG Features Table 46-4. JPEG Features Feature Decoder support Input data format JFIF file format 1.02 YCbCr 4:0:0, 4:2:0, 4:2:2 and 4:4:0 sampling formats Output data format YCbCr 4:0:0, 4:2:0, 4:2:2 and 4:4:0 semiplanar Supported image size 48x48 to 4672 x 3504 (16.4 million pixels) Step size 16 pixels Maximum data rate Up to 38 million pixels per second (1) Thumbnail decoding JPEG compressed thumbnails supported Error detection Supported Note: 46.3.1.5 1.
PAGE 1109
46.3.1.6 Post Processing Features Table 46-6. Postprocessing Features Input data format YCbCr 4:2:0 planar YCbCr 4:2:0 planar YCbCr 4:2:2 (YUYV) Input image source Internal source: VDEC decoder External source: e.g. a software decoder or camera interface Output data format YCbCr 4:2:0 semi-planar YCbCr 4:2:2 (YUYV) Fully configurable ARGB channel lengths and locations inside 32 bits, e.g.
PAGE 1110
Table 46-6. Postprocessing Features (Continued) RGB image color saturation adjustment Linear De-blocking filter for MPEG4 simple profile/H.263 Using a modified H.264 in-loop filter as a post-processing filter. Filtering has to be performed in combined mode. Image cropping /digital zoom User definable start position, height and width. Can be used with scaling to perform digital zoom. Usable only for JPEG or standalone mode.
PAGE 1111
Figure 46-2. Multi-format Decoder and External Memory Data Flow in VLC Mode External Memory H.264 NAL Unit Stream ARM Processor Core 1 2 3 AHB Bus Decoded Picture Buffer Post-Processed Picture Buffer 4 5 (6) 7 Multiformat HW Decoder Core 46.3.3 Decoder Data Flow, Software Performs Entropy Decoding (RLC Mode) In this case, the decoder software starts decoding the first picture by parsing the stream headers (1), and by performing entropy decoding.
PAGE 1112
Figure 46-3. Multi-format Decoder and External Memory Data Flow in RLC Mode External Memory ARM Processor Core H.
PAGE 1113
46.4 Product Dependencies 46.4.1 Power Management The Video Decoder requires a peripheral clock. The user has to enable UHP peripheral clock, bit (1 << AT91C_ID_VDEC) in PMC_PCER register. Software can reset the hardware synchronically by writing separate decoder and post-processor enable bits to zero. These enable bits are located in the memory-mapped registers and they can be used for terminating or restarting the decoding or post-processing at any time. 46.4.
PAGE 1114
46.5 Video Decoder User Interface (VDEC) User Interface The VDEC User interface is split into two interfaces. • One that concerns Post Processor and is common to all Decoder Modes, described by Video Post Processor Register Mapping. • One in which registers and fields depend on the Decoder Mode used. For best readability this document describes one Register Mapping for each Decoder Mode. The relations are given in Table 46-8. Table 46-8. Register Mapping vs.
PAGE 1115
Table 46-9.
PAGE 1116
46.6 Video Decoder Register Mapping (H.264) Table 46-10.
PAGE 1117
Table 46-10.
PAGE 1118
46.6.1 Name: Video Decoder ID Register VDEC_IDR Address: 0x00900000 Access: Read-Only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 PROD_ID 23 22 21 20 PROD_ID 15 14 13 12 MAJOR_VER 7 6 MINOR_VER 5 MINOR_VER 4 3 2 BUILD_VER • BUILD_VER: Build Version Build Version is 0x0. • MINOR_VER: Minor Version Minor Version is 0x88 • MAJOR_VER: Major Version Major Version is 0x0. • PROD_ID: Product ID Product ID is 0x8170.
PAGE 1119
46.6.2 Name: Decoder Interrupt Register VDEC_DIR Address: 0x00900004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 TO 17 JPEGSD 16 ISE 15 ASOD 14 SBE 13 BE 12 DR 11 – 10 – 9 – 8 ISET 7 – 6 – 5 – 4 ID 3 – 2 – 1 – 0 DE • DE: Decoder Enable 0: Disables Decoder. 1: Enables Decoder. Setting this bit high will start the decoding operation.
PAGE 1120
1: Input Stream Buffer is empty but the picture is not ready. Software must provide a new stream pointer to hardware. Hardware will not self-reset. • ASOD: ASO Detected 0: No ASO detected. 1: Interrupt status flag ASO detected. Hardware has encountered Arbitrary Slice Order tool in the input H.264 stream data, and software must perform entropy decoding. Hardware will self-reset. • ISE: Input Stream Error 0: No Error. 1: Interrupt Stream Error occurs.
PAGE 1121
46.6.3 Name: Decoder Device Configuration Register VDEC_DDCR Address: 0x00900008 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 HTI 22 – 21 DI_LE 20 – 19 – 18 AHB_BURST 17 DOPF 16 LAT_COMP 15 14 13 LAT_COMP 12 11 10 DDCGE 9 INTCE_LE 8 DO_LE 7 6 PRIOR 5 4 3 2 MAX_BURST_LEN 1 0 • MAX_BURST_LEN: Maximum Burst Length for Decoder Bus Transactions Valid values for AHB are 0, 1, 4, 8, 16 and 17. 0: INCR transfer type is used always.
PAGE 1122
• LAT_COMP: Decoder Latency Compensation Decoder latency compensation value in clock cycles. If the best case latency (from bus request to bus grant, or from data request to data receive) is known, the value can be written to these register bits used to compensate the delay. If the latency value is unknown, these bits should be written to zero. Note: Setting the compensation value higher than the best case latency can cause data corruption.
PAGE 1123
46.6.4 Name: Decoder Control Register 0 (Decoder Mode and Picture Type) VDEC_CTLR0 Address: 0x0090000C Access: Read-write 31 30 29 28 27 RLCEN 26 – 25 – 24 – DEC_MODE 23 PICMODE 22 PICSTRUCT 21 PICBEN 20 PICTYPE 19 PICFIELD 18 FORWMODE 17 – 16 REFFIELD 15 OUTDIS 14 FILTDIS 13 QUANT 12 MV 11 REFFIRST 10 – 9 – 8 HLOCK 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • HLOCK: HLOCK Enable 0: locked transfers disabled. 1: locked transfers enabled.
PAGE 1124
1: Top field • FORWMODE: Coding Mode of Forward Reference Picture 0: Progressive 1: Interlaced Note: For backward reference picture the coding mode is always the same as for current picture. • PICFIELD: Picture Field If field structure is enabled this bit informs which one of the fields is being decoded: 0: Bottom field 1: Top field • PICTYPE: Picture Type 0: Intra type (I) 1: Inter type (P) • PICBEN: B Picture Enable B picture enable for current picture: 0: Picture type is I or P depending on PICTYPE.
PAGE 1125
46.6.5 Name: Decoder Control Register 1 (Picture Parameters) VDEC_CTLR1 Address: 0x00900010 Access: Read-write 31 30 29 28 27 26 25 24 20 19 18 17 PIC_HEIGHT 16 PIC_WIDTH 23 PIC_WIDTH 22 21 15 14 13 PIC_HEIGHT 12 11 10 9 HEIGHT_OFF 8 7 HEIGHT_OFF 6 AVSM 5 TOPF 4 3 2 REF_FRAMES 1 0 WIDTH_OFF • REF_FRAMES: Number of Reference Frames/Semantics H.264: maximum number of short and long term reference frames in decoded picture buffer. VC-1: maximum number of semantics.
PAGE 1126
46.6.6 Name: Decoder Control Register 2 (H.264 Stream Decoding Table Selects) VDEC_CTLR2 Address: 0x00900014 Access: Read-write 31 30 23 22 29 28 STREAM_START_BIT 27 26 25 – 24 – 21 QPFILT_CB_OFF 20 19 18 17 QPFILT_CR_OFF 16 15 14 QPFILT_CR_OFF 13 – 12 – 11 – 10 – 9 – 8 – 7 – 5 – 4 – 3 – 2 – 1 – 0 FIELDPIC 6 – • FIELDPIC: Flag for Stream 1: Field picture flag exists in stream. • QPFILT_CR_OFF: Chrominance Offset Chroma Qp filter offset for Cr type.
PAGE 1127
46.6.7 Name: Decoder Control Register 3 (Stream Buffer Information) VDEC_CTLR3 Address: 0x00900018 Access: Read-write 31 ST_COD_EN 30 23 22 29 28 27 26 25 24 – 19 18 17 16 11 10 9 8 3 2 1 0 INIT_QP 21 20 STREAM_LEN 15 14 13 12 STREAM_LEN 7 6 5 4 STREAM_LEN • STREAM_LEN: Stream Length Amount of stream data bytes in input buffer.
PAGE 1128
46.6.8 Name: Decoder Control Register 4 (H.264 Control) VDEC_CTLR4 Address: 0x0090001C Access: Read-write 31 CABAC 30 BW 29 DIRMV_PRED 28 W_PRED 27 26 25 – 24 – 23 – 22 – 21 – 20 19 18 FRAME_NUM_LEN 17 16 15 14 13 12 11 10 9 8 3 2 1 0 W_BIPR FRAME_NUM 7 6 5 4 FRAME_NUM • FRAME_NUM: Frame Number Current Frame Number, used to identify short-term reference frames. Used in reference picture reordering.
PAGE 1129
46.6.9 Name: Decoder Control Register 5 (H.264 Control) VDEC_CTLR5 Address: 0x00900020 Access: Read-write 31 CONS_INTRA 30 FILT_CTRL 29 RD_PIC 28 T8X8FE 27 23 22 21 20 REF_PIC_LEN 19 15 14 13 12 26 25 24 18 17 16 IDREN 11 10 9 8 3 2 1 0 REF_PIC_LEN IDR_PIC_ID 7 6 5 4 IDR_PIC_ID • IDR_PIC_ID: IDR Picture Identifies IDR (instantaneous decoding refresh) picture. • IDREN: IDR Picture Enable IDR (instantaneous decoding refresh) picture flag.
PAGE 1130
46.6.10 Name: Decoder Control Register 6 (H.264 RLC Mode) VDEC_CTLR6 Address: 0x00900024 Access: Read-write 31 30 29 28 27 26 25 24 PPS_ID 23 15 22 21 REF_IDX1 20 19 18 17 REF_IDX0 16 14 13 – 12 – 11 – 10 – 9 – 8 – 6 5 4 3 2 1 0 REF_IDX0 7 POC_LEN • POC_LEN: Picture Order length Length of picture order count field in stream. • REF_IDX0: Maximum Reference Index 0 Specifies the maximum reference index that can be used while decoding inter predicted macro blocks.
PAGE 1131
46.6.11 Name: Decoder Control Register 6 (H.
PAGE 1132
46.6.12 Name: Differential Motion Vector Base Address (H.264, MPEG-4/H.
PAGE 1133
46.6.13 Name: Decoder Control Register 7 (H264, MPEG-4/H.263) VDEC_CTLR7 Address: 0x0090002C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address H.
PAGE 1134
46.6.14 Name: RLC/VLC Data Base Address VDEC_RLCVLCBA Address: 0x00900030 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address RLC_mode: Base address for RLC data (RLCEN = 1 in Decoder Control Register 0). VLC_mode: Stream start address/end address with byte precision (RLCEN = 0 in Decoder Control Register 0) STREAM_START_BIT field in Decoder Control Register 0.
PAGE 1135
46.6.15 Name: Decoded Picture Base Address (Video, JPEG Decoder Output Luma Picture) VDEC_PICTBA Address: 0x00900034 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Video: Base address for decoder output picture. Points directly to start of decoder output picture or field.
PAGE 1136
46.6.16 Name: Reference Picture Index Base Address (H.264) VDEC_PIDXBAx [x=0..
PAGE 1137
46.6.17 Name: Reference Picture Number Register 0 (H.
PAGE 1138
46.6.18 Name: Reference Picture Number Register 1 (H.
PAGE 1139
46.6.19 Name: Reference Picture Number Register 2 (H.
PAGE 1140
46.6.20 Name: Reference Picture Number Register 3 (H.
PAGE 1141
46.6.21 Name: Reference Picture Number Register 4 (H.
PAGE 1142
46.6.22 Name: Reference Picture Number Register 5 (H.
PAGE 1143
46.6.23 Name: Reference Picture Number Register 6 (H.
PAGE 1144
46.6.24 Name: Reference Picture Number Register 7 (H.
PAGE 1145
46.6.25 Name: Reference Picture Long Term Flag Register (H.264) VDEC_PLTFR Address: 0x00900098 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 LTF 23 22 21 20 LTF 15 14 13 12 LTF 7 6 5 4 LTF • LTF: Long Term Flag Long term reference picture index.
PAGE 1146
46.6.26 Name: Reference Picture Valid Flag Register (H.264) VDEC_PVFR Address: 0x0090009C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VF 23 22 21 20 VF 15 14 13 12 VF 7 6 5 4 VF • VF: Valid Flag Valid flag for reference picture index.
PAGE 1147
46.6.
PAGE 1148
46.6.28 Name: Direct Mode Motion Vector Base Address VDEC_DMMVBA Address: 0x009000A4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Not used in JPEG mode.
PAGE 1149
46.6.29 Name: H264 Initial Reference Picture List Register 0 (H.
PAGE 1150
46.6.30 Name: H264 Initial Reference Picture List Register 1 (H.
PAGE 1151
46.6.31 Name: H264 Initial Reference Picture List Register 2 (H.
PAGE 1152
46.6.32 Name: H264 Initial Reference Picture List Register 3 (H.
PAGE 1153
46.6.33 Name: H264 Initial Reference Picture List Register 4 (H.
PAGE 1154
46.6.34 Name: H264 Initial Reference Picture List Register 5 (H.
PAGE 1155
46.6.35 Name: Error Concealment Register VDEC_ECR Address: 0x009000C0 Access: Read-write 31 30 29 28 27 26 25 24 STARTMB_X 23 STARTMB_X 22 21 20 19 STARTMB_Y 18 17 16 15 STARTMB_Y 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • STARTMB_Y: Start MB from SW for Y Dimension Used in error concealment case. Not used in JPEG mode. • STARTMB_X: Start MB from SW for X Dimension Used in error concealment case. Not used in JPEG mode.
PAGE 1156
46.7 Video Decoder Register Mapping (MPEG-4/H.263) Table 46-11.
PAGE 1157
46.7.1 Name: Video Decoder ID Register VDEC_IDR Address: 0x00900000 Access: Read-Only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 PROD_ID 23 22 21 20 PROD_ID 15 14 13 12 MAJOR_VER 7 6 MINOR_VER 5 MINOR_VER 4 3 2 BUILD_VER • BUILD_VER: Build Version Build Version is 0x0. • MINOR_VER: Minor Version Minor Version is 0x88. • MAJOR_VER: Major Version Major Version is 0x0. • PROD_ID: Product ID Product ID is 0x8170.
PAGE 1158
46.7.2 Name: Decoder Interrupt Register VDEC_DIR Address: 0x00900004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 TO 17 JPEGSD 16 ISE 15 ASOD 14 SBE 13 BE 12 DR 11 – 10 – 9 – 8 ISET 7 – 6 – 5 – 4 ID 3 – 2 – 1 – 0 DE • DE: Decoder Enable 0: Disables Decoder. 1: Enables Decoder. Setting this bit high will start the decoding operation.
PAGE 1159
1: Input Stream Buffer is empty but the picture is not ready. Software must provide a new stream pointer to hardware. Hardware will not self-reset. • ASOD: ASO Detected 0: No ASO detected 1: Interrupt status flag ASO detected. Hardware has encountered Arbitrary Slice Order tool in the input H.264 stream data, and software must perform entropy decoding. Hardware will self-reset. • ISE: Input Stream Error 0: No error. 1: Interrupt stream error occurs.
PAGE 1160
46.7.3 Name: Decoder Device Configuration Register VDEC_DDCR Address: 0x00900008 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 HTI 22 – 21 DI_LE 20 – 19 – 18 AHB_BURST 17 DOPF 16 LAT_COMP 15 14 13 LAT_COMP 12 11 10 DDCGE 9 INTCE_LE 8 DO_LE 7 6 PRIOR 5 4 3 2 MAX_BURST_LEN 1 0 • MAX_BURST_LEN: Maximum Burst Length for Decoder Bus Transactions Valid values for AHB are 0, 1, 4, 8, 16 and 17. 0: INCR transfer type is used always.
PAGE 1161
• LAT_COMP: Decoder Latency Compensation Decoder latency compensation value in clock cycles. If the best case latency (from bus request to bus grant, or from data request to data receive) is known, the value can be written to these register bits used to compensate the delay. If the latency value is unknown, these bits should be written to zero. Note: Setting the compensation value higher than the best case latency can cause data corruption.
PAGE 1162
46.7.4 Name: Decoder Control Register 0 (Decoder Mode and Picture Type) VDEC_CTLR0 Address: 0x0090000C Access: Read-write 31 30 29 28 27 RLCEN 26 – 25 – 24 – DEC_MODE 23 PICMODE 22 PICSTRUCT 21 PICBEN 20 PICTYPE 19 PICFIELD 18 FORWMODE 17 – 16 REFFIELD 15 OUTDIS 14 FILTDIS 13 QUANT 12 MV 11 REFFIRST 10 – 9 – 8 HLOCK 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • HLOCK: HLOCK Enable 0: Locked transfers disabled. 1: Locked transfers enabled.
PAGE 1163
1: Top field • FORWMODE: Coding mode of forward reference picture 0: Progressive 1: Interlaced Note: For backward reference picture the coding mode is always same as for current picture. • PICFIELD: Picture field If field structure is enabled this bit informs which one of the fields is being decoded: 0: Bottom field 1: Top field • PICTYPE: Picture type 0: Intra type (I) 1: Inter type (P) • PICBEN: B Picture Enable B picture enable for current picture: 0: Picture type is I or P depending on PICTYPE.
PAGE 1164
46.7.5 Name: Decoder Control Register 1 (Picture Parameters) VDEC_CTLR1 Address: 0x00900010 Access: Read-write 31 30 29 28 27 26 25 24 20 19 18 17 PIC_HEIGHT 16 PIC_WIDTH 23 PIC_WIDTH 22 21 15 14 13 PIC_HEIGHT 12 11 10 9 HEIGHT_OFF 8 7 HEIGHT_OFF 6 AVSM 5 TOPF 4 3 2 REF_FRAMES 1 0 WIDTH_OFF • REF_FRAMES: Number of Reference Frames/Semantics H.264: maximum number of short and long term reference frames in decoded picture buffer. VC-1: maximum number of semantics.
PAGE 1165
46.7.6 Name: Decoder Control Register 2 (MPEG-4/H.263 Stream Decoding Table Selects) VDEC_CTLR2 Address: 0x00900014 Access: Read-write 31 30 29 28 STREAM_START_BIT 27 26 25 SYNCMAREN 24 QUANTYPE 23 22 21 QPFILT_OFF 19 18 17 VLC_THR 16 15 14 13 12 11 VOP_TIME_INC 10 9 8 7 6 5 4 2 1 0 20 3 VOP_TIME_INC • VOP_TIME_INC: VOP Time Increment VOP time increment resolution. • VLC_THR: VLC Threshold Intra DC VLC threshold.
PAGE 1166
46.7.7 Name: Decoder Control Register 3 (Stream Buffer Information) VDEC_CTLR3 Address: 0x00900018 Access: Read-write 31 ST_COD_EN 30 23 22 29 28 27 26 25 24 – 19 18 17 16 11 10 9 8 3 2 1 0 INIT_QP 21 20 STREAM_LEN 15 14 13 12 STREAM_LEN 7 6 5 4 STREAM_LEN • STREAM_LEN: Stream Length Amount of stream data bytes in input buffer.
PAGE 1167
46.7.8 Name: Decoder Control Register 6 (MPEG-4/H.
PAGE 1168
46.7.9 Name: Differential Motion Vector Base Address (H.264, MPEG-4/H.
PAGE 1169
46.7.10 Name: Decoder Control Register 7 (H264, MPEG-4/H.263) VDEC_CTLR7 Address: 0x0090002C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address H.
PAGE 1170
46.7.11 Name: RLC/VLC Data Base Address VDEC_RLCVLCBA Address: 0x00900030 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address RLC_mode: Base address for RLC data (RLCEN = 1 in Decoder Control Register 0). VLC_mode: Stream start address/end address with byte precision (RLCEN = 0 in Decoder Control Register 0) STREAM_START_BIT field in Decoder Control Register 0.
PAGE 1171
46.7.12 Name: Decoded Picture Base Address (Video, JPEG Decoder Output Luma Picture) VDEC_PICTBA Address: 0x00900034 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Video: Base address for decoder output picture. Points directly to start of decoder output picture or field.
PAGE 1172
46.7.13 Name: Reference Picture Index 0 Base Address VDEC_PIDXBA0 Addresses: 0x00900038 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Video: Base address for reference picture index 0.
PAGE 1173
46.7.14 Name: Reference Picture Index 1 Base Address (Video) VDEC_PIDXBA1 Addresses: 0x0090003C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for reference picture index 1.
PAGE 1174
46.7.15 Name: Reference Picture Index 2 Base Address (Video) VDEC_PIDXBA2 Addresses: 0x00900040 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for reference picture index 2.
PAGE 1175
46.7.16 Name: Reference Picture Index 3 Base Address (Video) VDEC_PIDXBA3 Addresses: 0x00900044 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for reference picture index 3.
PAGE 1176
46.7.17 Name: Reference Picture Index 4 Base Address (MPEG-4/H.
PAGE 1177
46.7.18 Name: Reference Picture Index 5 Base Address (MPEG-4/H.263 TRB/TRD Delta 0) VDEC_PIDXBA5 Addresses: 0x0090004C Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 25 TRB_PER_TRD 24 19 18 17 16 11 10 9 8 3 2 1 0 TRB_PER_TRD 15 14 13 12 TRB_PER_TRD 7 6 5 4 TRB_PER_TRD • TRB_PER_TRD: TRB per TRD Defines MPEG-4 reference distance syntax TRB/TRD when delta value 0 is used.
PAGE 1178
46.7.19 Name: Reference Picture Index 6 Base Address (MPEG-4/H.263 TRB/TRD Delta -1) VDEC_PIDXBA6 Addresses: 0x00900050 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 25 TRB_PER_TRD 24 19 18 17 16 11 10 9 8 3 2 1 0 TRB_PER_TRD 15 14 13 12 TRB_PER_TRD 7 6 5 4 TRB_PER_TRD • TRB_PER_TRD: TRB per TRD Defines MPEG-4 reference distance syntax TRB/TRD when delta value -1 is used.
PAGE 1179
46.7.20 Name: Reference Picture Index 7 Base Address (MPEG-4/H.263 TRB/TRD Delta 1) VDEC_PIDXBA7 Addresses: 0x00900054 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 25 TRB_PER_TRD 24 19 18 17 16 11 10 9 8 3 2 1 0 TRB_PER_TRD 15 14 13 12 TRB_PER_TRD 7 6 5 4 TRB_PER_TRD • TRB_PER_TRD: TRB per TRD Defines MPEG-4 reference distance syntax TRB/TRD when delta value 1 is used.
PAGE 1180
46.7.
PAGE 1181
46.7.22 Name: Direct Mode Motion Vector Base Address VDEC_DMMVBA Address: 0x009000A4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Not used in JPEG mode.
PAGE 1182
46.7.23 Name: Error Concealment Register VDEC_ECR Address: 0x009000C0 Access: Read-write 31 30 29 28 27 26 25 24 STARTMB_X 23 STARTMB_X 22 21 20 19 STARTMB_Y 18 17 16 15 STARTMB_Y 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • STARTMB_Y: Start MB from SW for Y Dimension. Used in error concealment case. Not used in JPEG mode. • STARTMB_X: Start MB from SW for X Dimension. Used in error concealment case. Not used in JPEG mode.
PAGE 1183
46.8 Video Decoder Register Mapping (JPEG) Table 46-12.
PAGE 1184
46.8.1 Name: Video Decoder ID Register VDEC_IDR Address: 0x00900000 Access: Read-Only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 PROD_ID 23 22 21 20 PROD_ID 15 14 13 12 MAJOR_VER 7 6 MINOR_VER 5 MINOR_VER 4 3 2 BUILD_VER • BUILD_VER: Build Version Build Version is 0x0 • MINOR_VER: Minor Version Minor Version is 0x88. • MAJOR_VER: Major Version Major Version is 0x0. • PROD_ID: Product ID Product ID is 0x8170.
PAGE 1185
46.8.2 Name: Decoder Interrupt Register VDEC_DIR Address: 0x00900004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 TO 17 JPEGSD 16 ISE 15 ASOD 14 SBE 13 BE 12 DR 11 – 10 – 9 – 8 ISET 7 – 6 – 5 – 4 ID 3 – 2 – 1 – 0 DE • DE: Decoder Enable 0: Disables decoder. 1: Enables decoder. Setting this bit high will start the decoding operation.
PAGE 1186
• SBE: Stream Buffer Empty 0: Stream Buffer is not empty. 1: Input Stream Buffer is empty but the picture is not ready. Software must provide a new stream pointer to hardware. Hardware will not self-reset. • ASOD: ASO Detected 0: No ASO detected. 1: Interrupt status flag ASO detected. Hardware has encountered Arbitrary Slice Order tool in the input H.264 stream data, and software must perform entropy decoding. Hardware will self-reset. • ISE: Input Stream Error 0: No Error. 1: Interrupt Stream Error occurs.
PAGE 1187
46.8.3 Name: Decoder Device Configuration Register VDEC_DDCR Address: 0x00900008 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 HTI 22 – 21 DI_LE 20 – 19 – 18 AHB_BURST 17 DOPF 16 LAT_COMP 15 14 13 LAT_COMP 12 11 10 DDCGE 9 INTCE_LE 8 DO_LE 7 6 PRIOR 5 4 3 2 MAX_BURST_LEN 1 0 • MAX_BURST_LEN: Maximum burst length for decoder bus transactions Valid values for AHB are 0, 1, 4, 8, 16 and 17.
PAGE 1188
• LAT_COMP: Decoder Latency Compensation Decoder latency compensation value in clock cycles. If the best case latency (from bus request to bus grant, or from data request to data receive) is known, the value can be written to these register bits used to compensate the delay. If the latency value is unknown, these bits should be written to zero. Note: Setting the compensation value higher than the best case latency can cause data corruption.
PAGE 1189
46.8.4 Name: Decoder Control Register 0 (Decoder Mode and Picture Type) VDEC_CTLR0 Address: 0x0090000C Access: Read-write 31 30 29 28 27 RLCEN 26 – 25 – 24 – DEC_MODE 23 PICMODE 22 PICSTRUCT 21 PICBEN 20 PICTYPE 19 PICFIELD 18 FORWMODE 17 – 16 REFFIELD 15 OUTDIS 14 FILTDIS 13 QUANT 12 MV 11 REFFIRST 10 – 9 – 8 HLOCK 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • HLOCK: HLOCK Enable 0: Locked transfers disabled. 1: Locked transfers enabled.
PAGE 1190
1: Top field • FORWMODE: Coding Mode of Forward Reference Picture 0: Progressive 1: Interlaced Note: For backward reference picture the coding mode is always the same as for current picture. • PICFIELD: Picture Field If field structure is enabled this bit informs which one of the fields is being decoded: 0: Bottom field 1: Top field • PICTYPE: Picture Type 0: Intra type (I) 1: Inter type (P) • PICBEN: B Picture Enable B picture enable for current picture: 0: Picture type is I or P depending on PICTYPE.
PAGE 1191
46.8.5 Name: Decoder Control Register 1 (Picture Parameters) VDEC_CTLR1 Address: 0x00900010 Access: Read-write 31 30 29 28 27 26 25 24 20 19 18 17 PIC_HEIGHT 16 PIC_WIDTH 23 PIC_WIDTH 22 21 15 14 13 PIC_HEIGHT 12 11 10 9 HEIGHT_OFF 8 7 HEIGHT_OFF 6 AVSM 5 TOPF 4 3 2 REF_FRAMES 1 0 WIDTH_OFF • REF_FRAMES: Number of reference frames/semantics H.264: maximum number of short and long term reference frames in decoded picture buffer. VC-1: maximum number of semantics.
PAGE 1192
46.8.6 Name: Decoder Control Register 2 (JPEG Stream Decoding Table Selects) VDEC_CTLR2 Address: 0x00900014 Access: Read-write 31 30 29 28 STREAM_START_BIT 27 26 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 11 10 9 MODE 8 7 FILL 6 END 5 ACCR 4 ACCB 3 DCCR 2 DCCB 1 – 0 – QTABLE • DCCB: DC Component of the Cb Defines which VLC table should be used for decoding DC components of the Cb.
PAGE 1193
• FILL: JPEG Fill Right 0: JPEG picture width is a multiple of 16. 1: JPEG picture width is a multiple of 8 pixels but not a multiple of 16 pixels. Can be set to 1 only for JPEG sampling format 0. HW must fill one block of zero pixel data to the right border of the picture.
PAGE 1194
46.8.7 Name: Decoder Control Register 3 (Stream Buffer Information) VDEC_CTLR3 Address: 0x00900018 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 STREAM_LEN 15 14 13 12 STREAM_LEN 7 6 5 4 STREAM_LEN • STREAM_LEN: Stream Length Amount of stream data bytes in input buffer.
PAGE 1195
46.8.8 Name: RLC/VLC Data Base Address VDEC_RLCVLCBA Address: 0x00900030 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address RLC_mode: Base address for RLC data (RLCEN = 1 in Decoder Control Register 0). VLC_mode: Stream start address/end address with byte precision (RLCEN = 0 in Decoder Control Register 0) STREAM_START_BIT field in Decoder Control Register 0.
PAGE 1196
46.8.9 Name: Decoded Picture Base Address (JPEG Decoder Output Luma Picture) VDEC_PICTBA Address: 0x00900034 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for decoder output luminance picture.
PAGE 1197
46.8.10 Name: Reference Picture Index 0 Base Address (JPEG Decoder Output Chroma Picture) VDEC_PIDXBA0 Addresses: 0x00900038 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address JPEG: Base address for decoder output chrominance picture (not needed if decoder output is not written).
PAGE 1198
46.8.11 Name: Reference Picture Index 1 Base Address (JPEG Control) VDEC_PIDXBA1 Addresses: 0x0090003C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 JPEG_SLICE • JPEG_SLICE: Base Address Height of the slice (multiple of 16 pixels) that HW decodes before interrupt. When slice is decoded, HW will raise an interrupt and reset external addresses back to base address.
PAGE 1199
46.8.
PAGE 1200
46.8.
PAGE 1201
46.8.
PAGE 1202
46.8.
PAGE 1203
46.8.
PAGE 1204
46.8.
PAGE 1205
46.8.
PAGE 1206
46.8.
PAGE 1207
46.8.
PAGE 1208
46.8.
PAGE 1209
46.8.
PAGE 1210
46.8.
PAGE 1211
46.9 Video Decoder Register Mapping (VC-1) Table 46-13.
PAGE 1212
46.9.1 Name: Video Decoder ID Register VDEC_IDR Address: 0x00900000 Access: Read-Only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 PROD_ID 23 22 21 20 PROD_ID 15 14 13 12 MAJOR_VER 7 6 MINOR_VER 5 MINOR_VER 4 3 2 BUILD_VER • BUILD_VER: Build Version Build Version is 0x0. • MINOR_VER: Minor Version Minor Version is 0x88. • MAJOR_VER: Major Version Major Version is 0x0. • PROD_ID: Product ID Product ID is 0x8170.
PAGE 1213
46.9.2 Name: Decoder Interrupt Register VDEC_DIR Address: 0x00900004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 TO 17 JPEGSD 16 ISE 15 ASOD 14 SBE 13 BE 12 DR 11 – 10 – 9 – 8 ISET 7 – 6 – 5 – 4 ID 3 – 2 – 1 – 0 DE • DE: Decoder Enable 0: Disables decoder. 1: Enables decoder. Setting this bit high will start the decoding operation.
PAGE 1214
• SBE: Stream Buffer Empty 0: Stream Buffer is not empty 1: Input Stream Buffer is empty but the picture is not ready. Software must provide a new stream pointer to hardware. Hardware will not self-reset. • ASOD: ASO Detected 0: No ASO detected. 1: Interrupt status flag ASO detected. Hardware has encountered Arbitrary Slice Order tool in the input H.264 stream data, and software must perform entropy decoding. Hardware will self-reset. • ISE: Input Stream Error 0: No error. 1: Interrupt stream error occurs.
PAGE 1215
46.9.3 Name: Decoder Device Configuration Register VDEC_DDCR Address: 0x00900008 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 HTI 22 – 21 DI_LE 20 – 19 – 18 AHB_BURST 17 DOPF 16 LAT_COMP 15 14 13 LAT_COMP 12 11 10 DDCGE 9 INTCE_LE 8 DO_LE 7 6 PRIOR 5 4 3 2 MAX_BURST_LEN 1 0 • MAX_BURST_LEN: Maximum Burst Length for Decoder Bus Transactions Valid values for AHB are 0, 1, 4, 8, 16 and 17. 0: INCR transfer type is used always.
PAGE 1216
• LAT_COMP: Decoder Latency Compensation Decoder latency compensation value in clock cycles. If the best case latency (from bus request to bus grant, or from data request to data receive) is known, the value can be written to these register bits used to compensate the delay. If the latency value is unknown, these bits should be written to zero. Note: Setting the compensation value higher than the best case latency can cause data corruption.
PAGE 1217
46.9.4 Name: Decoder Control Register 0 (Decoder Mode and Picture Type) VDEC_CTLR0 Address: 0x0090000C Access: Read-write 31 30 29 28 27 RLCEN 26 – 25 – 24 – DEC_MODE 23 PICMODE 22 PICSTRUCT 21 PICBEN 20 PICTYPE 19 PICFIELD 18 FORWMODE 17 – 16 REFFIELD 15 OUTDIS 14 FILTDIS 13 QUANT 12 MV 11 REFFIRST 10 – 9 – 8 HLOCK 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • HLOCK: HLOCK Enable 0: Locked transfers disabled. 1: Locked transfers enabled.
PAGE 1218
1: Top field • FORWMODE: Coding Mode of Forward Reference Picture 0: Progressive 1: Interlaced Note: For backward reference picture the coding mode is always same as for current picture. • PICFIELD: Picture Field If field structure is enabled this bit informs which one of the fields is being decoded: 0: Bottom field 1: Top field • PICTYPE: Picture Type 0: Intra type (I) 1: Inter type (P) • PICBEN: B Picture Enable B picture enable for current picture: 0: Picture type is I or P depending on PICTYPE.
PAGE 1219
46.9.5 Name: Decoder Control Register 1 (Picture Parameters) VDEC_CTLR1 Address: 0x00900010 Access: Read-write 31 30 29 28 27 26 25 24 20 19 18 17 PIC_HEIGHT 16 PIC_WIDTH 23 PIC_WIDTH 22 21 15 14 13 PIC_HEIGHT 12 11 10 9 HEIGHT_OFF 8 7 HEIGHT_OFF 6 AVSM 5 TOPF 4 3 2 REF_FRAMES 1 0 WIDTH_OFF • REF_FRAMES: Number of Reference Frames/Semantics VC-1: maximum number of semantics. • TOPF: Top Field Top field is first information for VC-1.
PAGE 1220
46.9.6 Name: Decoder Control Register 2 (VC-1 Stream Decoding Table Selects) VDEC_CTLR2 Address: 0x00900014 Access: Read-write 31 30 29 28 STREAM_START_BIT 27 26 25 SYNCMAREN 24 Q_PROFILE 23 DQBI 22 IS_REDU 21 – 20 FAST_UVMC 19 – 18 – 17 TDC_TAB 16 CAC_TAB 15 CAC_TAB 14 13 12 11 MB_MODE_TAB 10 9 8 7 MV_TAB 6 3 2 YAC_TAB 5 MB_TAB 4 MV_TAB 1 2MV_TAB 0 4MV_TAB • 4MV_TAB: 4MV Block Pattern Block pattern table select in interlaced pictures when 4mv macroblock.
PAGE 1221
Is current picture range reduced: 0: No 1: Yes • DQBI: Quantization Step Size 0: Each macroblock may take on any quantization step size (STREAMD). 1: Only PQUANT and ALT_PQUANT allowed in Decoder control register 4. Used if DQUANT =1 in Decoder control register 4 and Q_PROFILE =1. • Q_PROFILE: Quantization Profile 0: Picture edges 1: All macroblocks • SYNCMAREN: Synchronization Markers Enable 0: Synch markers are not used. 1: Synch markers are used.
PAGE 1222
46.9.7 Name: Decoder Control Register 3 (Stream Buffer Information) VDEC_CTLR3 Address: 0x00900018 Access: Read-write 31 ST_COD_EN 30 23 22 29 28 27 26 25 24 – 19 18 17 16 11 10 9 8 3 2 1 0 INIT_QP 21 20 STREAM_LEN 15 14 13 12 STREAM_LEN 7 6 5 4 STREAM_LEN • STREAM_LEN: Stream Length Amount of stream data bytes in input buffer.
PAGE 1223
46.9.8 Name: Decoder Control Register 4 (VC-1 Control) VDEC_CTLR4 Address: 0x0090001C Access: Read-write 31 BIT_PLAN0 30 BIT_PLAN1 29 BIT_PLAN2 28 27 26 ALT_PQUANT 25 24 23 22 21 20 19 TTMBF 18 17 PQ_INDEX 16 13 – 12 BILIN 11 UNIQ 10 HALFQP 9 8 5 VC1_ADV 4 – 3 – 2 – 1 – DQ_EDGES 15 14 PQ_INDEX 7 – 6 DQUANT TTFRM 0 – • VC1_ADV: VC-1 Advance Profile 1: VC-1 advanced profile enable.
PAGE 1224
• DQ_EDGES: Quantized Edge Specifies which edges will be quantized using ALT_PQUANT, if Q_PROFILE set to picture edges in Video Decoder Control Register 3. 0: Left edge 2: Top edge 4: Right edge 8: Bottom edge Other: Reserved • ALT_PQUANT: Alternative PQUANT Used if DQUANT = 1. • BIT_PLAN2: Bitplane Mode Enable 2 Bitplane mode enable for corresponding element. • BIT_PLAN1: Bitplane Mode Enable 1 Bitplane mode enable for corresponding element.
PAGE 1225
46.9.9 Name: Decoder Control Register 5 (VC-1 Control) VDEC_CTLR4 Address: 0x0090001C Access: Read-write 31 30 29 28 27 SCALE_FACTOR 26 25 24 23 22 21 REF-DIST_FWD 20 19 18 17 REF_DIST_BWD 16 15 14 REF_DIST_BWD 13 – 12 – 11 – 10 – 9 – 8 – 7 – 5 – 4 – 3 – 2 – 1 – 0 – 6 – • REF_DIST_BWD: VC-1 Reference Distance for BWD Direction VC-1 reference distance for BWD direction (used for B type pictures).
PAGE 1226
46.9.10 Name: Decoder Control Register 6 (VC-1 Intensity Control 0) VDEC_CTLR6 Address: 0x00900024 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 ICOMP0 19 18 17 16 11 10 9 8 3 2 1 0 IScale0 15 14 13 12 ISHIFT0 7 6 5 4 ISHIFT0 • ISHIFT0: IShift Value IShift value used for VC-1 intensity compensation. • IScale0: IScale Value IScale value used for VC-1 intensity compensation. • ICOMP0: Intensity Compensation Value Intensity compensation 0 enable.
PAGE 1227
46.9.11 Name: Differential Motion Vector Base Address (VC-1 Intensity Control 1) VDEC_DMVBA Address: 0x00900028 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 ICOMP1 19 18 17 16 11 10 9 8 3 2 1 0 IScale1 15 14 13 12 ISHIFT1 7 6 5 4 ISHIFT1 • ISHIFT1: IShift Value IShift value used for VC-1 intensity compensation. • IScale1: IScale Value IScale value used for VC-1 intensity compensation.
PAGE 1228
46.9.12 Name: Decoder Control Register 7 (VC-1 Intensity Control 2) VDEC_CTLR7 Address: 0x0090002C Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 ICOMP2 19 18 17 16 11 10 9 8 3 2 1 0 IScale2 15 14 13 12 ISHIFT2 7 6 5 4 ISHIFT2 • ISHIFT2: Ishift Value IShift value used for VC-1 intensity compensation. • IScale2: IScale Value IScale value used for VC-1 intensity compensation. • ICOMP2: Intensity Compensation Value Intensity compensation 2 enable.
PAGE 1229
46.9.13 Name: RLC/VLC Data Base Address VDEC_RLCVLCBA Address: 0x00900030 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address RLC_mode: Base address for RLC data (RLCEN = 1 in Decoder Control Register 0). VLC_mode: Stream start address/end address with byte precision (RLCEN = 0 in Decoder Control Register 0) STREAM_START_BIT field in Decoder Control Register 0.
PAGE 1230
46.9.14 Name: Decoded Picture Base Address (Video, JPEG Decoder Output Luma Picture) VDEC_PICTBA Address: 0x00900034 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Video: Base address for decoder output picture. Points directly to start of decoder output picture or field.
PAGE 1231
46.9.15 Name: Reference Picture Index 0 Base Address (Video, JPEG Decoder Output Chroma Picture) VDEC_PIDXBA0 Addresses: 0x00900038 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Video: Base address for reference picture index 0.
PAGE 1232
46.9.16 Name: Reference Picture Index 1 Base Address (Video) VDEC_PIDXBA1 Addresses: 0x0090003C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for reference picture index 1.
PAGE 1233
46.9.17 Name: Reference Picture Index 2 Base Address (Video) VDEC_PIDXBA2 Addresses: 0x00900040 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for reference picture index 2.
PAGE 1234
46.9.18 Name: Reference Picture Index 3 Base Address (Video) VDEC_PIDXBA3 Addresses: 0x00900044 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for reference picture index 3.
PAGE 1235
46.9.
PAGE 1236
• DIFF_MV_RANGE: Differential Motion Vector Range Specifies maximum differential motion vector length (advanced profile only). • RED_REF_EN: Range Reduce Enable Reference picture range reduce enable: 0: Disabled 1: Enabled • PIC_4M: 4M Pictures Allowed 0: Only 1 MV/MB. 1: 4 MV/MB allowed. • HEADER_LEN: Header Length Length of picture header in bits.
PAGE 1237
46.9.20 Name: Reference Picture Index 5 Base Address VDEC_PIDXBA5 Addresses: 0x0090004C Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 ICOMP3 19 18 17 16 11 10 9 8 3 2 1 0 IScale3 15 14 13 12 ISHIFT3 7 6 5 4 ISHIFT3 • ISHIFT3: Ishift Value IShift value used for VC-1 intensity compensation. • IScale3: IScale Value IScale value used for VC-1 intensity compensation. • ICOMP3: Intensity Compensation Value Intensity compensation 3 enable.
PAGE 1238
46.9.21 Name: Reference Picture Index 6 Base Address (VC-1 Intensity Control 4) VDEC_PIDXBA6 Addresses: 0x00900050 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 ICOMP4 19 18 17 16 11 10 9 8 3 2 1 0 IScale4 15 14 13 12 ISHIFT4 7 6 5 4 ISHIFT4 • ISHIFT4: Ishift Value IShift value used for VC-1 intensity compensation. • IScale4: IScale Value IScale value used for VC-1 intensity compensation.
PAGE 1239
46.9.22 Name: Reference Picture Index 13 Base Address (VC-1) VDEC_PIDXBA13 Addresses: 0x0090006C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address VC-1: Base address for VC-1 bitplane mb control.
PAGE 1240
46.9.23 Name: Direct Mode Motion Vector Base Address VDEC_DMMVBA Address: 0x009000A4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Not used in JPEG mode.
PAGE 1241
46.9.24 Name: Error Concealment Register VDEC_ECR Address: 0x009000C0 Access: Read-write 31 30 29 28 27 26 25 24 STARTMB_X 23 STARTMB_X 22 21 20 19 STARTMB_Y 18 17 16 15 STARTMB_Y 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • STARTMB_Y: Start MB from SW for Y Dimension. Used in error concealment case. Not used in JPEG mode. • STARTMB_X: Start MB from SW for X Dimension. Used in error concealment case. Not used in JPEG mode.
PAGE 1242
46.10 Video Decoder Register Mapping (MPEG-2/MPEG-1) Table 46-14.
PAGE 1243
46.10.1 Name: Video Decoder ID Register VDEC_IDR Address: 0x00900000 Access: Read-Only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 PROD_ID 23 22 21 20 PROD_ID 15 14 13 12 MAJOR_VER 7 6 MINOR_VER 5 MINOR_VER 4 3 2 BUILD_VER • BUILD_VER: Build Version Build Version is 0x0. • MINOR_VER: Minor Version Minor Version is 0x88. • MAJOR_VER: Major Version Major Version is 0x0. • PROD_ID: Product ID Product ID is 0x8170.
PAGE 1244
46.10.2 Name: Decoder Interrupt Register VDEC_DIR Address: 0x00900004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 TO 17 – 16 ISE 15 ASOD 14 SBE 13 BE 12 DR 11 – 10 – 9 – 8 ISET 7 – 6 – 5 – 4 ID 3 – 2 – 1 – 0 DE • DE: Decoder Enable 0: Disables decoder. 1: Enables decoder. Setting this bit high will start the decoding operation.
PAGE 1245
1: Input Stream Buffer is empty but the picture is not ready. Software must provide a new stream pointer to hardware. Hardware will not self-reset. • ASOD: ASO Detected 0: No ASO detected. 1: Interrupt status flag ASO detected. Hardware has encountered Arbitrary Slice Order tool in the input H.264 stream data, and software must perform entropy decoding. Hardware will self-reset. • ISE: Input Stream Error 0: No error. 1: Interrupt stream error occurs.
PAGE 1246
46.10.3 Name: Decoder Device Configuration Register VDEC_DDCR Address: 0x00900008 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 HTI 22 – 21 DI_LE 20 – 19 – 18 AHB_BURST 17 DOPF 16 LAT_COMP 15 14 13 LAT_COMP 12 11 10 DDCGE 9 INTCE_LE 8 DO_LE 7 6 PRIOR 5 4 3 2 MAX_BURST_LEN 1 0 • MAX_BURST_LEN: Maximum burst length for decoder bus transactions Valid values for AHB are 0, 1, 4, 8, 16 and 17. 0: INCR transfer type is used always.
PAGE 1247
• LAT_COMP: Decoder Latency Compensation Decoder latency compensation value in clock cycles. If the best case latency (from bus request to bus grant, or from data request to data receive) is known, the value can be written to these register bits used to compensate the delay. If the latency value is unknown, these bits should be written to zero. Note: Setting the compensation value higher than the best case latency can cause data corruption.
PAGE 1248
46.10.4 Name: Decoder Control Register 0 (Decoder Mode And Picture Type) VDEC_CTLR0 Address: 0x0090000C Access: Read-write 31 30 29 28 27 – 26 – 25 – 24 – DEC_MODE 23 PICMODE 22 PICSTRUCT 21 PICBEN 20 PICTYPE 19 PICFIELD 18 FORWMODE 17 – 16 – 15 OUTDIS 14 FILTDIS 13 QUANT 12 MV 11 REFFIRST 10 – 9 – 8 HLOCK 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • HLOCK: HLOCK Enable 0: Locked transfers disabled. 1: Locked transfers enabled.
PAGE 1249
Note: For backward reference picture, the coding mode is always same as for current picture. • PICFIELD: Picture Field If field structure is enabled, this bit informs which one of the fields is being decoded: 0: Bottom field 1: Top field • PICTYPE: Picture Type 0: Intra type (I) 1: Inter type (P) • PICBEN: B Picture Enable B picture enable for current picture: 0: Picture type is I or P depending on PICTYPE. 1: Picture type is BI (vc1)/D (mpeg1) or B depending on PICTYPE.
PAGE 1250
46.10.5 Name: Decoder Control Register 1 (Picture Parameters) VDEC_CTLR1 Address: 0x00900010 Access: Read-write 31 30 29 28 27 26 25 24 PIC_WIDTH 23 PIC_WIDTH 22 – 21 – 20 – 19 – 18 17 PIC_HEIGHT 16 15 14 13 PIC_HEIGHT 12 11 10 – 9 – 8 – 7 – 6 AVSM 5 – 4 – 3 – 2 – 1 – 0 – • AVSM: Alternative Vertical Scan Method Indicates alternative vertical scan method used for interlaced frames. • PIC_HEIGHT: Picture Height Picture height in macroblocks = ((height in pixels+15)/16).
PAGE 1251
46.10.6 Name: Decoder Control Register 2 (MPEG-2/MPEG-1 Stream Decoding Table Selects) VDEC_CTLR2 Address: 0x00900014 Access: Read-write 31 30 29 28 STREAM_START_BIT 27 26 25 – 24 Q_SCALE 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 CON_MV 3 2 1 VLC_TAB 0 PRED_DCT INTRA_DC • PRED_DCT: Frame Prediction Semantics Defines frame prediction semantics for MPEG2/MPEG1.
PAGE 1252
46.10.7 Name: Decoder Control Register 3 (Stream Buffer Information) VDEC_CTLR3 Address: 0x00900018 Access: Read-write 31 ST_COD_EN 30 23 22 29 28 27 26 25 24 – 19 18 17 16 11 10 9 8 3 2 1 0 INIT_QP 21 20 STREAM_LEN 15 14 13 12 STREAM_LEN 7 6 5 4 STREAM_LEN • STREAM_LEN: Stream Length Amount of stream data bytes in input buffer.
PAGE 1253
46.10.8 Name: RLC/VLC Data Base Address VDEC_RLCVLCBA Address: 0x00900030 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address RLC_mode: Base address for RLC data (RLCEN = 1 in Decoder Control Register 0). VLC_mode: Stream start address/end address with byte precision (RLCEN = 0 in Decoder Control Register 0) STREAM_START_BIT field in Decoder Control Register 0.
PAGE 1254
46.10.9 Name: Decoded Picture Base Address (Video) VDEC_PICTBA Address: 0x00900034 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Video: Base address for decoder output picture. Points directly to start of decoder output picture or field.
PAGE 1255
46.10.10 Reference Picture Index 0 Base Address (Video) Name: VDEC_PIDXBA0 Addresses: 0x00900038 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Video: Base address for reference picture index 0.
PAGE 1256
46.10.11 Reference Picture Index 1 Base Address (Video) Name: VDEC_PIDXBA1 Addresses: 0x0090003C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for reference picture index 1.
PAGE 1257
46.10.12 Reference Picture Index 2 Base Address (Video) Name: VDEC_PIDXBA2 Addresses: 0x00900040 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for reference picture index 2.
PAGE 1258
46.10.13 Reference Picture Index 3 Base Address (Video) Name: VDEC_PIDXBA3 Addresses: 0x00900044 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for reference picture index 3.
PAGE 1259
46.10.14 Reference Picture Index 4 Base Address (MPEG-2/MPEG-1) Name: VDEC_PIDXBA4 Addresses: 0x00900048 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 SCANF 18 17 FW_HOR_BN 16 15 FW_HOR_BN 14 13 12 11 10 9 BW_HOR_BN 8 7 BW_HOR_BN 6 4 3 2 ACC_FW 1 ACC_BW 0 – FW_VER_BN 5 BW_VER_BN • ACC_BW: Forward Motion Vector Backward motion vector Y resolution. 0: 1 pel 1: 1/2 pel • ACC_FW: Forward Motion Vector Forward motion vector Y resolution.
PAGE 1260
46.10.
PAGE 1261
46.10.
PAGE 1262
46.10.17 Error Concealment Register Name: VDEC_ECR Address: 0x009000C0 Access: Read-write 31 30 29 28 27 26 25 24 STARTMB_X 23 STARTMB_X 22 21 20 19 STARTMB_Y 18 17 16 15 STARTMB_Y 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • STARTMB_Y: Start MB from SW for Y Dimension. Used in error concealment case. Not used in JPEG mode. • STARTMB_X: Start MB from SW for X Dimension. Used in error concealment case. Not used in JPEG mode.
PAGE 1263
46.11 Video Post-processor Register Mapping (All Decoders) Table 46-15.
PAGE 1264
46.11.1 Name: Post-Processor Interrupt Register Access: VDEC_PPIR Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 BE 12 PPR 11 – 10 – 9 – 8 ISET 7 – 6 – 5 – 4 ID 3 – 2 – 1 PIPE 0 PPE • PPE: Post-processor Standalone Enable 0: Disables post-processor. 1: Enables post-processor. Setting this bit high will start the post-processing operation. Hardware will reset this bit when a picture is processed.
PAGE 1265
0: No error. 1: A bus error has occurred. When high, hardware has received an error response from the bus while accessing external memory. This is a fatal error possibly caused by the incorrect allocation of post-processor linear memory. Hardware will self-reset.
PAGE 1266
46.11.2 Name: Post Processor Device Configuration Register Access: VDEC_PPCR Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 HLOCK 14 – 13 – 12 – 11 – 10 – 9 AHB_BURST 8 PPDCGE 7 PPI_LE 6 PPO_LE 5 – 4 3 2 MAX_BURST_LEN 1 0 • MAX_BURST_LEN: Maximum burst length for post-processor bus transactions Valid values for AHB are 0, 1, 4, 8 and 16. 0: AHB INCR transfer type is used always. 1: AHB SINGLE transfer type is used always.
PAGE 1267
46.11.3 Name: Post Processor Deinterlace Control Register Access: VDEC_PPDCR Read-write 31 DEINT_EN 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 DEINT_THRD 20 DEINT_THRD 15 BLEND_EN 14 13 12 11 EDGE_DET_VAL 10 9 8 7 6 5 4 3 2 1 0 EDGE_DET_VAL • EDGE_DET_VAL: Edge Detect Value Used for deinterlacing. • BLEND_EN: Blend Enable for Deinterlacing • DEINT_THRD: Threshold Value Used in Deinterlacing • DEINT_EN: Deinterlace Enable.
PAGE 1268
46.11.4 Name: Access: 31 Post Processor Input Y Top Field Picture Base Address VDEC_PIYTBA Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for post-processing input luminance picture. If PP input picture is fetched from fields, this base address is used to point to top field of the picture. Used in external mode only.
PAGE 1269
46.11.5 Name: Access: 31 Post Processor Input Cb Top Field Picture Base Address VDEC_PICBTBA Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for post-processing input Cb picture or for both chrominance pictures (if Chrominance interleaved). If PP input picture is fetched from fields, this base address is used to point to top field of the picture. Used in external mode only.
PAGE 1270
46.11.6 Name: Access: 31 Post Processor Input Cr Picture Base Address VDEC_PICRBA Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for post-processing input cr picture.
PAGE 1271
46.11.7 Name: Access: 31 Post Processor Output Y Picture Base Address VDEC_POYBA Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for post-processing output picture (luminance/YUYV/RGB).
PAGE 1272
46.11.8 Name: Access: 31 Post Processor Output C Picture Base Address VDEC_POCBA Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address Base address for post-processing output chrominance picture (interleaved chrominance).
PAGE 1273
46.11.9 Name: Access: 31 Post Processor Contrast Adjustment Register VDEC_CAR Read-write 30 29 28 27 26 20 – 19 18 12 11 25 24 17 16 THRD1 23 BA 22 – 21 – 15 14 13 OFFSET2 10 9 OFFSET2 7 6 5 8 OFFSET1 4 3 2 1 0 OFFSET1 • OFFSET1: Offset Value 1 Used with contrast adjusting. • OFFSET2: Offset Value 2 Used with contrast adjusting. • THRD1: Threshold Value 1 Used with contrast adjusting.
PAGE 1274
46.11.10 Post Processor Contrast Adjustment and Color Conversion Register Name: VDEC_CACCR Access: Read-write 31 – 30 – 29 – 23 22 21 28 – 27 20 19 26 25 18 17 COEFF_A2 15 14 13 24 COEFF_A2 16 COEFF_A1 12 11 10 9 8 3 2 1 0 COEFF_A1 7 6 5 4 THRD2 • THRD2: Threshold Value 2 Used with contrast adjusting. • COEFF_A1: Coefficient a1 Coefficient a1, used with Y pixel to calculate all color components.
PAGE 1275
46.11.11 Post Processor Color Conversion Register Name: VDEC_CCR Access: Read-write 31 – 30 – 23 22 29 28 27 26 21 20 19 18 COEFF_D 15 14 25 24 17 16 COEFF_D COEFF_C 13 12 11 10 9 COEFF_C 7 6 5 8 COEFF_B 4 3 2 1 0 COEFF_B • COEFF_B: Coefficient b Coefficient b, used with Cr to calculate red component value. • COEFF_C: Coefficient c Coefficient c, used with Cr to calculate green component value.
PAGE 1276
46.11.12 Post Processor Color Conversion and Rotation Mode Register Name: VDEC_CCRMR Access: Read-write 31 – 30 – 29 28 23 22 CROPSTART_X 21 20 14 13 15 27 26 CROPSTART_X 19 ROT_MODE 18 11 10 12 25 17 6 5 16 COEFF_F 9 COEFF_F 7 24 8 COEFF_E 4 3 2 1 0 COEFF_E • COEFF_E: Coefficient e Coefficient e, used with Cb to calculate blue component value.
PAGE 1277
46.11.13 Post Processor Input Picture Size and Cropping Register Name: VDEC_PISCR Access: Read-write 31 30 29 28 27 CROPSTART_Y 23 – 22 21 20 RANGEMAP_COEFF 15 14 13 12 26 25 24 19 18 17 – 16 – 11 10 9 8 3 2 1 0 IN_PICT_H 7 6 5 4 IN_PICT_W • IN_PICT_W: Input Picture Width PP input picture width in MBs. Can be cropped from a bigger input picture in external mode. • IN_PICT_H: Input Picture Height PP input picture height in MBs.
PAGE 1278
46.11.14 Post Processor Input Y Bottom Field Picture Base Address Name: VDEC_PIYBBA Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address PP input Y base for bottom field.
PAGE 1279
46.11.15 Post Processor Input Cb Bottom Field Picture Base Address Name: VDEC_PICBBBA Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – BA 23 22 21 20 BA 15 14 13 12 BA 7 6 5 4 BA • BA: Base Address PP input C base for bottom field (mixed chrominance).
PAGE 1280
46.11.16 Post Processor R and G Padding and Scaling Ratio Register 0 Name: VDEC_RGPSRR0 Access: Read-write 31 MAP_Y_EN 30 MAP_C_EN 29 YCBCR_RAN 28 RGBBY32 27 26 25 24 23 RGB_R_PADD 22 21 20 RGB_G_PADD 19 18 17 16 SCALE_W_RATIO 15 14 13 12 11 SCALE_W_RATIO 10 9 8 7 6 5 4 3 SCALE_W_RATIO 2 1 0 RGB_R_PADD • SCALE_W_RATIO: Scaling Ratio for Width (outputw-1/inputw-1) • RGB_G_PADD: Padding for G-component Amount of ones that will be padded in front of the G-component.
PAGE 1281
46.11.17 Post Processor B Padding and Scaling Ratio Register 1 Name: VDEC_BPSRR1 Access: Read-write 31 – 30 – 29 28 PP_IN_STRUCT 27 23 V_SCAL_MOD 22 21 15 14 7 6 26 25 20 RGB_B_PADD 19 18 17 16 SCALE_H_RATIO 13 12 11 SCALE_H_RATIO 10 9 8 5 4 3 SCALE_H_RATIO 2 1 0 H_SCAL_MOD 24 V_SCAL_MOD • SCALE_H_RATIO: Scaling Ratio for Height (outputh-1/inputh-1) • RGB_B_PADD: Padding for B-component Amount of ones that will be padded in front of the B-component.
PAGE 1282
46.11.18 Post Processor Scaling Ratio Register 2 Name: VDEC_SRR2 Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 W_SCALE_INV 23 22 21 20 W_SCALE_INV 15 14 13 12 H_SCALE_INV 7 6 5 4 H_SCALE_INV • H_SCALE_INV: Inverse Scaling for Height Inverse scaling ratio for height or cv (inputh-1 / outputh-1). • W_SCALE_INV: Inverse Scaling for Width Inverse scaling ratio for width, or ch (inputw-1 / outputw-1).
PAGE 1283
46.11.
PAGE 1284
46.11.
PAGE 1285
46.11.
PAGE 1286
46.11.22 Post Processor Control Register Name: VDEC_CTLR Access: 31 23 Read-write 30 IN_FORMAT 29 22 21 28 27 OUT_FORMAT 26 19 18 17 16 20 25 24 OUT_H OUT_H 15 OUT_H 14 7 6 13 12 11 OUT_W 10 9 8 5 4 3 – 2 – 1 CROP8_R_EN 0 CROP8_D_EN OUT_W • CROP8_D_EN: Crop 8 Down Pixel PP input picture height is not 16 pixels multiple. Only 8 pixel rows of the most down MB of the unrotated input picture is used for PP input.
PAGE 1287
5: YCbCr 4:2:0 Semi-planar in tiled format (supported only in external mode). 6: YCbCr 4:4:0 Semi-planar (supported only in pipelined mode, possible for jpeg only).
PAGE 1288
46.11.23 Post Processor Mask 1 Start Coordinate Register Name: VDEC_M1STR Access: Read-write 31 – 30 – 29 – 28 – 27 23 MAP_COEFF 22 M1_AB_EN 21 20 19 15 14 13 M1_START_Y 12 7 6 5 4 26 25 24 18 17 16 11 10 9 M1_START_X 8 3 2 1 0 RMV M1_START_Y M1_START_X • M1_START_X: Mask 1 X Start Horizontal start pixel for mask area 1. Defines the x coordinate. Coordinate 0, 0 means the up-left corner in PP output luminance picture.
PAGE 1289
46.11.24 Post Processor Mask 2 Start Coordinate Register Name: VDEC_M2STR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 M2_AB_EN 21 20 19 18 17 16 15 14 13 M2_START_Y 12 11 10 9 M2_START_X 8 7 6 5 4 3 2 1 0 M2_START_Y M2_START_X • M2_START_X: Mask 2 X Start Horizontal start pixel for mask area 2. Defines the x coordinate. Coordinate 0,0 means the up-left corner in PP output luminance picture.
PAGE 1290
46.11.25 Post Processor Mask 1 Size and PP Original Width Register Name: VDEC_M1SZOWR Access: 31 Read-write 30 29 28 27 26 25 24 18 17 16 11 10 9 M1_END_X 8 3 2 1 0 PP_ORIG_W 23 PP_ORI_W 22 M1_EN 21 20 15 14 13 M1_END_Y 12 7 6 5 4 19 M1_END_Y M1_END_X • M1_END_X: Mask 1 X End Mask 1 end coordinate x in pixels (inside of PPD output picture). Range must be between [Mask1StartCoordinateX, ScaledWidth].
PAGE 1291
46.11.26 Post Processor Mask 2 Size Register Name: VDEC_M2SZR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 M2_EN 21 20 19 18 17 16 15 14 13 M2_END_Y 12 11 10 9 M2_END_X 8 7 6 5 4 3 2 1 0 M2_END_Y M2_END_X • M2_END_X: Mask 2 X end Mask 2 end coordinate x in pixels (inside of PP output picture). Range must be between [Mask2StartCoordinateX, ScaledWidth]. • M2_START_Y: Mask 2 Y end Mask 2 end coordinate y in pixels (inside of PP output picture).
PAGE 1292
46.11.27 Post Processor Picture-in-Picture Register 0 Name: VDEC_PIPR0 Access: Read-write 31 – 30 – 29 RIGHT_EN 28 LEFT_EN 27 UP_EN 26 DOWN_EN 25 24 23 22 21 20 19 18 17 16 11 – 10 9 DOWN_CROSS 8 3 2 1 0 UP_CROSS UP_CROSS 15 UP_CROSS 14 – 13 – 12 – 7 6 5 4 DOWN_CROSS • DOWN_CROSS: Down Cross Amount of downward overcross (vertical pixels outside of display from the down side). Range must be between [0, ScaledHeight].
PAGE 1293
46.11.28 Post Processor Dithering and Picture-in-Picture Register 1 Name: VDEC_DPIPR1 Access: Read-write 31 30 29 DITH_SEL_R 28 27 26 25 – 24 – 18 17 16 11 10 9 LEFT_CROSS 8 3 2 1 0 DITH_SEL_G DITH_SEL_B 23 – 22 – 21 20 15 14 13 RIGHT_CROSS 12 7 6 5 4 19 RIGHT_CROSS LEFT_CROSS • LEFT_CROSS: Left Cross Amount of left side overcross (Horizontal pixels outside of display from the left side). Range must be between [0, ScaledWidth].
PAGE 1294
46.11.29 Post Processor Display Width Register Name: VDEC_DWR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DISP_WIDTH 3 2 DISP_WIDTH • DISP_WIDTH: Display Width Width of the display in pixels. Maximum is 1920 (HDTV).
PAGE 1295
46.11.30 Post Processor Alpha Blending GUI 1 Component Base Address Name: VDEC_ABGUI1BA Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – AB_GUI1_BA 23 22 21 20 AB_GUI1_BA 15 14 13 12 AB_GUI1_BA 7 6 5 4 AB_GUI1_BA • AB_GUI1_BA: Alpha Blending GUI 1 Base Address Base address for alpha blending input 1 (if mask1 is used in alpha blending mode). Format of data is 24-bit RGB/YCbCr and endian/swap -mode is as in PP input.
PAGE 1296
46.11.31 Post Processor Alpha Blending GUI 2 Component Base Address Name: VDEC_ABGUI2BA Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – AB_GUI2_BA 23 22 21 20 AB_GUI2_BA 15 14 13 12 AB_GUI2_BA 7 6 5 4 AB_GUI1_BA • AB_GUI2_BA: Alpha Blending GUI 2 Base Address Base address for alpha blending input 2 (if mask2 is used in alpha blending mode). Format of data is 24-bit RGB/YCbCr and endian/swap -mode is as in PP input.
PAGE 1297
47. SAM9M10 Electrical Characteristics 47.1 Absolute Maximum Ratings Table 47-1. Absolute Maximum Ratings* *NOTICE: Operating Temperature (Industrial)................-40°C to + 85°C Junction Temperature-..................................................125°C Storage Temperature-...................................60°C to + 150°C Voltage on Input Pins with Respect to Ground......-0.3V to VDDIO+0.
PAGE 1298
Table 47-2. DC Characteristics (Continued) VVDDIOM1 DC Supply EBI I/Os VVDDIOP0 DC Supply Peripheral I/Os VVDDIOP1 1.95/3.6 V 1.65 3.6 V DC Supply Peripheral I/Os 1.65 3.6 V VVDDIOP2 DC Supply ISI 1.65 3.6 V VVDDANA DC Supply Analog 3.0 3.
PAGE 1299
Table 47-2. ISC 47.3 DC Characteristics (Continued) On VVDDCORE = 1.0V, MCK = 0 Hz, excluding POR TA = 25°C All inputs driven TMS, TDI, TCK, NRST = 1 TA = 85°C On VVDDBU = 3.3V, Logic cells consumption, excluding POR TA = 25°C All inputs driven WKUP = 0 TA = 85°C 30 mA 120 Static Current 9 μA 25 Power Consumption • Typical power consumption of PLLs, Slow Clock and Main Oscillator. • Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup.
PAGE 1300
These figures represent the power consumption estimated on the power supplies. Table 47-3. Power Consumption for Different Modes Mode Conditions Consumption Unit Active ARM Core clock is 400 MHz. MCK is 133 MHz. All peripheral clocks activated. onto AMP2 130 mA Idle Idle state, waiting an interrupt. All peripheral clocks de-activated. onto AMP2 55 mA Ultra low power ARM Core clock is 500 Hz. All peripheral clocks de-activated.
PAGE 1301
47.4 Clock Characteristics 47.4.1 Processor Clock Characteristics Table 47-5. Processor Clock Waveform Parameters Symbol Parameter Conditions 1/(tCPPCK) Processor Clock Frequency VDDCORE = 0.9V T = 85°C 47.4.2 Min Max Units 125(1) 400 MHz Min Max Units 125(1) 133 MHz Master Clock Characteristics Table 47-6. Master Clock Waveform Parameters Symbol Parameter Conditions 1/(tCPMCK) Master Clock Frequency VDDCORE = 0.
PAGE 1302
SAM9M10 XIN XOUT GNDOSC CCRYSTAL CLEXT CLEXT 47.5.1 Crystal Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. Table 47-8. Crystal Characteristics Symbol Parameter ESR Max Unit Equivalent Series Resistor Rs 80 Ω CM Motional Capacitance 9 fF CS Shunt Capacitance 7 pF 47.5.2 XIN Clock Characteristics Table 47-9.
PAGE 1303
47.6 32 kHz Oscillator Characteristics Table 47-10. 32 kHz Oscillator Characteristics Symbol Parameter Conditions 1/(tCP32KHz) Crystal Oscillator Frequency CCRYSTAL32 Load Capacitance CLEXT32(2) External Load Capacitance Min Crystal @ 32.768 kHz Unit kHz 6 12.5 pF CCRYSTAL32 = 6 pF 6 pF CCRYSTAL32 = 12.5 pF 19 pF 40 RS = 50 kΩ(1) Startup Time RS = 100 kΩ(1) Notes: Max 32 768 Duty Cycle tST Typ 60 % CCRYSTAL32 = 6 pF 400 ms CCRYSTAL32 = 12.
PAGE 1304
47.6.2 XIN32 Clock Characteristics Table 47-12.
PAGE 1305
47.8 PLL Characteristics Table 47-14. PLLA Characteristics Symbol Parameter Conditions Min FOUT Output Frequency Refer to following table FIN Input Frequency IPLL Current Consumption T Startup Time Typ Max Unit 400 800 MHz 2 32 MHz 9 mA 1 μA 50 μs active mode 7 standby mode The following configuration of ICPLLA and OUTA must be done for each PLLA frequency range. Table 47-15. PLLA Frequency Regarding ICPLLA and OUTA 47.8.
PAGE 1306
47.9 I/Os Criteria used to define the maximum frequency of the I/Os: • Output duty cycle (40%-60%) • Minimum output swing: 100 mV to VDDIO - 100 mV • Addition of rising and falling time inferior to 75% of the period Table 47-17. I/O Characteristics Symbol Parameter FreqMax Conditions Min Max Units 3.3V domain (1) Max. external load = 20 pF Max. external load = 40 pF 66 34 MHz 1.8V domain(2) Max. external load = 20 pF Max.
PAGE 1307
47.10.3 Dynamic Power Consumption Table 47-20. Dynamic Power Consumption Symbol Parameter IBIAS Bias current consumption on VBG IVDDUTMII IVDDUTMIC Note: Conditions Min Typ Max Unit 0.7 0.
PAGE 1308
47.11 Touch Screen ADC (TSADC) Table 47-21. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency 10-bit resolution mode Startup Time Return from Idle Mode Min (1) Typ Max Units 13.2 MHz 40 μs 0.5 μs Track and Hold Acquisition Time (TTH) ADC Clock = 13.2 MHz Conversion Time (TCT) ADC Clock = 13.2 MHz(1) 1.75 μs (1) 440 kSPS Throughput Rate Note: ADC Clock = 13.2 MHz 1. The Track-and-Hold Acquisition Time is given by: TTH (ns) = 500 + ( 0.
PAGE 1309
47.12 Core Power Supply POR Characteristics Table 47-25. Power-On-Reset Characteristics Symbol Parameter Conditions Min Typ Max Units Vth+ Threshold Voltage Rising Minimum Slope of +2.0V/30ms 0.5 0.7 0.89 V Vth- Threshold Voltage Falling 0.4 0.6 0.85 V TRES Reset Time 30 70 130 μs 47.12.1 47.12.2 Power Sequence Requirements The SAM9M10 board design must comply with the power-up guidelines below to guarantee reliable operation of the device.
PAGE 1310
– T1 = 66 μs – T2 = 352 μs In conclusion, establish VDDIOP and VDDIOM first, and VDDCORE last to ensure reliable operation of the device. VDDOSC, VDDPLL, VDDUTMII and VDDUTMIC must be started at any time but before VDDCORE to ensure correct behavior of the ROM code. 47.13 SMC Timings 47.13.1 Timing Conditions SMC Timings are given for MAX corners. Timings are given assuming a capacitance load on data, control and address pads: Table 47-26. Capacitance Load Corner Supply MAX MIN 3.3V 50pF 5 pF 1.
PAGE 1311
Table 47-28. SMC Read Signals - NCS Controlled (READ_MODE= 1) (Continued) HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold =0) SMC5 NBS0/A0, NBS1, NBS2/A1, NBS3, A2 A25 Valid before NRD High SMC6 NCS low before NRD High SMC7 NRD Pulse Width (nrd setup + nrd pulse)* tCPMCK 15.4 (nrd setup + nrd pulse)* tCPMCK - 15.5 ns (nrd setup + nrd pulse - ncs rd setup) * tCPMCK -14.7 (nrd setup + nrd pulse ncs rd setup) * tCPMCK 14.7 ns nrd pulse * tCPMCK - 0.5 nrd pulse * tCPMCK - 0.2 ns Table 47-29.
PAGE 1312
Table 47-30. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) (Continued) Min Symbol Parameter SMC20 NWE High to NCS Inactive (1) 1.8V Supply 3.3V Supply Units (nwe hold - ncs wr hold)* tCPMCK 3.2 (nwe hold - ncs wr hold)* tCPMCK - 4.0 ns 1.4 ns NO HOLD SETTINGS (nwe hold = 0) NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25, NCS change(1) SMC21 Notes: 1.6 1. hold length = total cycle duration - setup duration - pulse duration.
PAGE 1313
Figure 47-3. SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC26 SMC24 A0/A1/NBS[3:0]/A2-A25 SMC13 SMC13 NRD SMC14 NCS SMC14 SMC9 SMC8 SMC10 SMC23 SMC11 SMC22 SMC26 D0 - D15 SMC27 SMC25 NWE NCS Controlled READ with NO HOLD NCS Controlled READ with HOLD NCS Controlled WRITE Figure 47-4.
PAGE 1314
47.14 DDRSDRC Timings The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR modules. DDR2, LP-DDR and SDR timings are specified by the JEDEC standard. Supported speed grade limitations: • DDR2-400 limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#) • LP-DDR (1.8V, 30pF on data/control, 10pF on CK) Tcyc = 5.0 ns, Fmax = 125 MHz Tcyc = 6.0 ns, Fmax = 110 MHz Tcyc = 7.5 ns, Fmax = 95 MHz • SDR-100 (3.3V, 50pF on data/control, 10pF on CK) • SDR-133 (3.
PAGE 1315
Table 47-32. Capacitance Load for MISO, SPCK and MOSI (product dependent) Corner 47.15.1.3 Supply MAX MIN 3.3V 40 pF 5 pF 1.8V 20 pF 5 pF Timing Extraction Figure 47-5. SPI Master Mode 1 and 2 SPCK SPI0 SPI1 MISO SPI2 MOSI Figure 47-6.
PAGE 1316
Figure 47-7. SPI Slave Mode 0 and 3 NPCS0 SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 47-8. SPI Slave Mode 1 and 2 NPCS0 SPI13 SPI12 SPCK SPI9 MISO SPI10 SPI11 MOSI Figure 47-9.
PAGE 1317
Table 47-33. SPI Timings with 3.3V Peripheral Supply Symbol Parameter Cond Min Max Units 66 MHz Master Mode SPISPCK SPI Clock SPI0 MISO Setup time before SPCK rises SPI1 14.6 ns MISO Hold time after SPCK rises 0 ns SPI2 SPCK rising to MOSI 0 SPI3 MISO Setup time before SPCK falls SPI4 SPI5 0.2 ns 14.3 ns MISO Hold time after SPCK falls 0 ns SPCK falling to MOSI 0 0.6 ns 15.1 ns Slave Mode SPI6 SPCK falling to MISO 4.6 SPI7 MOSI Setup time before SPCK rises 0.
PAGE 1318
Table 47-34. SPI Timings with 1.8V Peripheral Supply (Continued) Symbol Parameter SPI9 Cond Min Max Units SPCK rising to MISO 5.5 18.7 ns SPI10 MOSI Setup time before SPCK falls 0.5 ns SPI11 MOSI Hold time after SPCK falls 1.4 ns SPI12 NPCS0 setup to SPCK rising 17.4 ns SPI13 NPCS0 hold after SPCK falling 15.5 ns SPI14 NPCS0 setup to SPCK falling 17.8 ns SPI15 NPCS0 hold after SPCK rising 15.3 ns SPI16 NPCS0 falling to MISO valid 5.4 17.7 ns Figure 47-10.
PAGE 1319
47.15.2.2 Timing Extraction Figure 47-11. SSC Transmitter, TK and TF in Output TK (CKI =0) TK (CKI =1) SSC0 TF/TD Figure 47-12. SSC Transmitter, TK in Input and TF in Output TK (CKI =0) TK (CKI =1) SSC1 TF/TD Figure 47-13.
PAGE 1320
Figure 47-14. SSC Receiver RK and RF in Input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 47-15. SSC Receiver, RK in Input and RF in Output RK (CKI=1) RK (CKI=0) SSC8 SSC9 RD SSC10 RF Figure 47-16. SSC Receiver, RK and RF in Output RK (CKI=1) RK (CKI=0) SSC11 SSC12 RD SSC13 RF Figure 47-17.
PAGE 1321
Table 47-36. SSC Timings with 3.3V Peripheral Supply Symbol Parameter Cond Min Max Units 0 (2) 4.0 (2) ns Transmitter SSC0 TK edge to TF/TD (TK output, TF output) SSC1 TK edge to TF/TD (TK input, TF output) SSC2 TF setup time before TK edge (TK output) SSC3 TF hold time after TK edge (TK output) (1) SSC4 TK edge to TF/TD (TK output, TF input) SSC5 TF setup time before TK edge (TK input) SSC6 TF hold time after TK edge (TK input) (1) SSC7 3.7 (2) 13.6 (2) ns 14.
PAGE 1322
Table 47-37. SSC Timings with 1.8V Peripheral Supply (Continued) Symbol Parameter Cond Min Max Unit s Receiver SSC8 RF/RD setup time before RK edge (RK input) SSC9 RF/RD hold time after RK edge (RK input) Notes: ns tCPMCK SSC10 RK edge to RF (RK input) SSC11 RF/RD setup time before RK edge (RK output) SSC12 RF/RD hold time after RK edge (RK output) SSC13 2.4 5.4 ns (2) 21.5 (2) 18.6 - tCPMCK ns tCPMCK - 5.1 RK edge to RF (RK output) 0 (2) ns ns 5.3 (2) ns 1.
PAGE 1323
47.15.3.2 Timing Extraction Figure 47-19. ISI Timing Diagram PIXCLK 3 DATA[7:0] VSYNC HSYNC Valid Data Valid Data 1 Valid Data 2 Table 47-39. ISI Timings with 3.3V Peripheral Supply Symbol Parameter Min Max Units ISI1 DATA/VSYNC/HSYNC setup time 1.1 ns ISI2 DATA/VSYNC/HSYNC hold time 2.0 ns ISI3 PIXCLK frequency 80 MHz Max Units Table 47-40. ISI Timings with 1.8V Peripheral Supply Symbol Parameter Min ISI1 DATA/VSYNC/HSYNC setup time 1.
PAGE 1324
47.15.5.2 Timing Constraints The Ethernet controller must satisfy the timings of MAX corner standards given in Table 47-42 and Table 47-43. Table 47-42. EMAC Signals Relative to EMDC Symbol Parameter EMAC1 Setup for EMDIO from EMDC rising 13.5 EMAC2 Hold for EMDIO from EMDC rising 10 EMAC3 EMDIO toggling from EMDC falling 0 (1) Notes: Min (ns) Max (ns) 2 (1) 1. For EMAC output signals, Min and Max access time are defined.
PAGE 1325
Figure 47-21. EMAC MII Mode EMDC EMAC1 EMAC3 EMAC2 EMDIO EMAC4 EMAC5 EMAC6 EMAC7 ECOL ECRS ETXCK EMAC8 ETXER EMAC9 ETXEN EMAC10 ETX[3:0] ERXCK EMAC11 EMAC12 ERX[3:0] EMAC13 EMAC14 EMAC15 EMAC16 ERXER ERXDV Table 47-44.
PAGE 1326
Figure 47-22. EMAC RMII Timings EREFCK EMAC21 ETXEN EMAC22 ETX[1:0] EMAC23 EMAC24 ERX[1:0] EMAC25 EMAC26 EMAC27 EMAC28 ERXER ECRSDV 47.15.6 UART in SPI Mode 47.15.6.1 Timing Conditions Timings are given assuming a capacitance load on MISO, SPCK and MOSI: Table 47-45. Capacitance Load for MISO, SPCK and MOSI (product dependent) Corner 47.15.6.2 Supply MAX MIN 3.3V 40pF 0 pF 1.8V 20 pF 0 pF Timing Extraction Figure 47-23.
PAGE 1327
Figure 47-24. UART SPI Slave Mode NPCS0 SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 47-25. SPI Slave Mode - NPCS Timings SPI15 SPI14 SPI6 SPCK (CPOL = 0) SPI12 SPI13 SPI9 SPCK (CPOL = 1) SPI16 MISO Table 47-46. UART SPI Timings with 3.3V Peripheral Supply Symbol Parameter Cond Min Max Units Master Mode SPI0 SPCK Period SPI1 Input Data Setup Time 17.2 ns SPI2 Input Data Hold Time 0 ns SPI3 Chip Select Active to Serial Clock 3.5 ns SPI4 Output Data Setup Time 0.
PAGE 1328
Table 47-46. UART SPI Timings with 3.3V Peripheral Supply (Continued) Symbol Parameter SPI9 SPCK rising to MISO SPI10 MOSI Setup time before SPCK falls SPI11 MOSI Hold time after SPCK falls SPI12 Cond Min Max Units 4.7 (1) 17.1 (1) ns 0.4 ns 0 ns NPCS0 setup to SPCK rising 10.3 ns SPI13 NPCS0 hold after SPCK falling 2.0 ns SPI14 NPCS0 setup to SPCK falling 10.7 ns SPI15 NPCS0 hold after SPCK rising 2.0 ns SPI16 NPCS0 falling to MISO valid Notes: 16.0 ns 1.
PAGE 1329
48. SAM9M10 Mechanical Characteristics 48.1 Package Drawings Figure 48-1.
PAGE 1330
Table 48-1. Soldering Information Ball Land 0.4 mm +/- 0.05 Soldering Mask Opening 0.275 mm +/- 0.03 Table 48-2. Device and 324-ball TFBGA Package Maximum Weight 400 mg Table 48-3. 324-ball TFBGA Package Characteristics Moisture Sensitivity Level Table 48-4. 3 Package Reference JEDEC Drawing Reference MO-210 JESD97 Classification e1 This package respects the recommendations of the NEMI User Group. 48.
PAGE 1331
48.3 Marking All devices are marked with the Atmel logo and the ordering code.
PAGE 1332
49. SAM9M10 Ordering Information Table 49-1.
PAGE 1333
50. SAM9M10 Errata 50.1 50.1.1 SAM9M10 Errata - Rev. A Parts Boot ROM 50.1.1.1 Boot ROM: NAND Flash boot does not support ECC Correction The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the boot ROM does not feature ECC correction on a NAND Flash. Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free.
PAGE 1334
Perform the ECC computation by software. 50.1.3.4 Unsupported hardware ECC on 16-bit Nand Flash Hardware ECC on 16-bit Nand Flash is not supported. Problem Fix/Workaround Perform the ECC by software. 50.1.4 Pulse Width Modulation Controller (PWM) 50.1.4.1 PWM: Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register. Problem Fix/Workaround None 50.1.5 RSTC: Software Reset During DDRAM Accesses 50.1.5.
PAGE 1335
The data is sent but there is not any toggle of the TF line Problem Fix/Workaround Transmit STTDLY must be different from 0. 50.1.7.2 SSC: Unexpected delay on TD output When SSC is configured with the following conditions: • TCMR.STTDLY more than 0 • RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge • RFMR.FSOS = None (input) • TCMR.START = Receive Start Unexpected delay of 2 or 3 system clock cycles is added to TD output. Problem Fix/Workaround None 50.1.
PAGE 1336
around on the data rate is dependent on the error rate observed in the application but can be such that streaming data at high rates becomes impractical. 50.1.10 USB High Speed Host Port (UHPHS) and Device Port (UDPHS) 50.1.10.1 UHPHS/UDPHS: USB does not start after power-up The USB may not start properly at first use after power-up. Booting out of the internal ROM fixes this issue because the workaround below is applied in the ROM Code. Problem Fix/Workaround There are two possible workarounds. 1.
PAGE 1337
50.2 50.2.1 SAM9M10 Errata - Rev. B Parts Boot ROM 50.2.1.1 Boot ROM: NAND Flash boot does not support ECC Correction The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the boot ROM does not feature ECC correction on a NAND Flash. Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free.
PAGE 1338
50.2.3.4 Unsupported hardware ECC on 16-bit Nand Flash Hardware ECC on 16-bit Nand Flash is not supported. Problem Fix/Workaround Perform the ECC by software. 50.2.4 Pulse Width Modulation Controller (PWM) 50.2.4.1 PWM: Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register. Problem Fix/Workaround None 50.2.5 RSTC: Software Reset During DDRAM Accesses 50.2.5.
PAGE 1339
Transmit STTDLY must be different from 0. 50.2.7.2 SSC: Unexpected delay on TD output When SSC is configured with the following conditions: • TCMR.STTDLY more than 0 • RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge • RFMR.FSOS = None (input) • TCMR.START = Receive Start Unexpected delay of 2 or 3 system clock cycles is added to TD output. Problem Fix/Workaround None 50.2.8 Touch Screen (TSADCC) 50.2.8.
PAGE 1340
– c- Restart the UTMIPLL and wait for the PLL Lock bit Warning: When booting out of the internal ROM, this workaround is not implemented and therefore SAMBA will not be functional.
PAGE 1341
50.3 50.3.1 SAM9M10 Errata - Rev. C Parts Boot ROM 50.3.1.1 Boot ROM: NAND Flash boot does not support ECC Correction The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the boot ROM does not feature ECC correction on a NAND Flash. Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free.
PAGE 1342
50.3.4 Pulse Width Modulation Controller (PWM) 50.3.4.1 PWM: Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register. Problem Fix/Workaround None 50.3.5 RSTC: Software Reset During DDRAM Accesses 50.3.5.1 Software reset during DDRAM access When a software reset (CPU and peripherals) occurs during DDRAM read access, the CPU will stop the DDRAM clock. The DDRAM maintains the data on the bus until the clock restarts.
PAGE 1343
• RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge • RFMR.FSOS = None (input) • TCMR.START = Receive Start Unexpected delay of 2 or 3 system clock cycles is added to TD output. Problem Fix/Workaround None 50.3.8 Touch Screen (TSADCC) 50.3.8.1 TSADCC: Pen detect accuracy is not good Depending on LCD panels, the pen detect is noisy, leading to an unpredictable behavior. Problem Fix/Workaround An additional resistor solves the problem.
PAGE 1344
/* First enable the UTMI PLL */ AT91C_BASE_PMC->CKGR_UCKR |= (AT91C_CKGR_UCKR_PLLCOUNT & (0x3 << 20)) | AT91C_CKGR_UCKR_UPLLEN; tmp =0; while (((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_SR_LOCKU) == 0) && (tmp++ < DELAY)); /* Disable the PLLUTMI and wait 10µs min*/ AT91C_BASE_PMC->CKGR_UCKR &= ~AT91C_CKGR_UCKR_UPLLEN; tmp = 0; while(tmp++ < DELAY2); // DELAY2 must be defined to fit the 10µs min; /* Re- enable the UTMI PLL and wait for the PLL lock status*/ AT91C_BASE_PMC->CKGR_UCKR |= (AT91C_CKGR_UCKR_PLLCOUNT &
PAGE 1345
Revision History In the tables that follow, the most recent version appears first. The initials “rfo” indicate changes requested by product experts, or made during proof reading as part of the approval process. Doc. Rev 6355F Comments Change Request Ref. Ordering Codes: Table 49-1, “SAM9M10 Ordering Information”, added AT91SAM9M10C-CU and MRL C 8551 Product Overview: Table 3-1 “Signal Description List” , added open drain comment to NRST line. Section 1.
PAGE 1346
. Doc. Rev 6355E Change Request Ref. Comments Errata: Added Boot errata related to AT45-series SPI DataFlash: Section 50.1.1.2 “Boot ROM: Boot issue on AT45series SPI dataflash” and Section 50.2.1.2 “Boot ROM: Boot issue on AT45-series SPI dataflash” Removed section 50.2.8 ‘USB High Speed Host Port (UHPHS) and Device Port (UDPHS)’: solved in Rev. B Added Section 50.1.5 “RSTC: Software Reset During DDRAM Accesses” and Section 50.2.5 “RSTC: Software Reset During DDRAM Accesses” Doc.
PAGE 1347
Doc. Rev 6355C Change Request Ref. Comments Introduction Product Line/Product naming convention changed - ARM-based MPU / SAM9M10 Section 5.1 “Power Supplies”, replaced ground pin names by GNDIOM, GNDCORE, GNDANA, GNDIOP, GNDBU, GNDOSC, GNDUTMI. Reorganized text describing GND association to power supply pins rfo 7332 rfo Clock Generator Figure 25-2 and Figure 25-5, GND changed to GNDOSC. 7332 DDRSDRC “DDRSDRC Timing Parameter 1 Register” ,TXSNR field, “Number of cycles is between 0 and 255”.
PAGE 1348
Doc. Rev 6355B Change Request Ref. Comments Bus Matrix 7171 “12-layer” Matrix instead of “11-layer” in Section 19. “Bus Matrix (MATRIX)” DDRSDRC In Section 22.8.6 “DDRSDRC Timing Parameter 2 Register”, - TRTP bitfield reset value (0 --> 2) changed. - 0 and 15’ cycles changed into ‘0 and 7’ in ”TRTP: Read to Precharge”. - TXARD (-->2), TXARDS (-->6), and TRPA (-->0) reset values changed. In Section 22.8.7 “DDRSDRC Low-power Register”, UPD_MR bitfield added to the table at [21:20]. In Section 22.5.4.
PAGE 1349
Table of Contents Features ..................................................................................................... 1 1 Description ................................................................................................ 2 2 Block Diagram .......................................................................................... 3 3 Signal Description .................................................................................... 4 4 Package and Pinout .......................
PAGE 1350
9.9 Bus Interface Unit ..................................................................................................49 10 SAM9M10 Debug and Test .................................................................... 51 10.1 Description ...........................................................................................................51 10.2 Embedded Characteristics ..................................................................................51 10.3 Block Diagram ............................
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15.2 Embedded Characteristics ................................................................................111 15.3 Block Diagram ...................................................................................................111 15.4 Functional Description .......................................................................................111 15.5 Periodic Interval Timer (PIT) User Interface ......................................................113 16 Watchdog Timer (WDT) ........................
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21.2 I/O Lines Description .........................................................................................185 21.3 Multiplexed Signals ............................................................................................185 21.4 Application Example ..........................................................................................186 21.5 Product Dependencies ......................................................................................186 21.6 External Memory Mapping .......
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24.3 Block Diagram ...................................................................................................323 24.4 Functional Description .......................................................................................323 24.5 Peripheral DMA Controller (PDC) User Interface ..............................................326 25 Clock Generator ................................................................................... 337 25.1 Description ............................................
PAGE 1354
28.1 Description .........................................................................................................399 28.2 Embedded Characteristics ................................................................................399 28.3 Block Diagram ...................................................................................................400 28.4 Application Block Diagram .................................................................................401 28.5 Signal Description ..........
PAGE 1355
32.3 List of Abbreviations ..........................................................................................576 32.4 Block Diagram ...................................................................................................576 32.5 Application Block Diagram .................................................................................577 32.6 Product Dependencies ......................................................................................577 32.7 Functional Description .........
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35.9 SD/SDIO Card Operation ..................................................................................718 35.10 CE-ATA Operation ...........................................................................................719 35.11 HSMCI Boot Operation Mode ..........................................................................720 35.12 HSMCI Transfer Done Timings .......................................................................722 35.13 MultiMedia Card Interface (MCI) User Interface ........
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40.3 Block Diagram ...................................................................................................922 40.4 Signal Description ..............................................................................................923 40.5 Product Dependencies ......................................................................................923 40.6 Analog-to-digital Converter Functional Description ...........................................924 40.7 Touch Screen ...............................
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44.2 True Random Number Generator (TRNG) User Interface ..............................1074 45 LCD Controller (LCDC) ...................................................................... 1081 45.1 Description .......................................................................................................1081 45.2 Embedded Characteristics ..............................................................................1081 45.3 Block Diagram ..............................................................
PAGE 1359
47.10 USB HS Characteristics ................................................................................1346 47.11 Touch Screen ADC (TSADC) ........................................................................1348 47.12 Core Power Supply POR Characteristics ......................................................1349 47.13 SMC Timings .................................................................................................1350 47.14 DDRSDRC Timings .............................................
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SAM9M10 [DATASHEET] 6355F–ATARM–12-Mar-13 xii
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Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.