Datasheet

21
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
Figure 6-2. USB Selection
6.5 DMA Controller
z Two Masters
z Embeds 8 channels
z 64 bytes/FIFO for Channel Buffering
z Linked List support with Status Write Back operation at End of Transfer
z Word, HalfWord, Byte transfer support.
z memory to memory transfer
z Peripheral to memory
z Memory to peripheral
The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the
peripherals below. The hardware interface numbers are also given below in Table 6-7.
HS
Transceiver
DMA
HS
USB
DMA
HS EHCI
FS OHCI
PA PB
HS
Transceiver
1
0
EN UDPHS
Table 6-7. DMA Channel Definition
Instance Name T/R
DMA Channel HW
interface Number
MCI0 TX/RX 0
SPI0 TX 1
SPI0 RX 2
SPI1 TX 3
SPI1 RX 4
SSC0 TX 5
SSC0 RX 6
SSC1 TX 7
SSC1 RX 8
AC97C TX 9
AC97C RX 10
MCI1 TX/RX 13