Datasheet

SAM9G45 [Summary]

6438IS–ATARM–12-Feb-13

Table 6-5 summarizes the Slave Memory Mapping for each connected Master, depending on the Remap status (RCBx

bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and the BMS state at reset.

Table 6-4. SAM9G45 Masters to Slaves Access with DDRMP_DIS = 1 (default)

Master 01234 & 567891011

Slave

ARM

926 Instr.

ARM

926 Data PDC

USB

HOST

OHCI DMA

ISI

DMA

LCD

DMA

Ethernet

MAC

USB

Device HS

USB Host

EHCI Reserved

0 Internal SRAM 0 XXXXXX- XXX -

Internal ROM X X X -----X--

UHP OHCI X X ---------

UHP EHCI X X ---------

LCD User Int. X X ---------

UDPHS RAM X X ---------

Reserved X X ---------

2 DDR Port 0 - - --------X

3 DDR Port 1 - - ----X----

4 DDR Port 2 X - XXXX - XXX -

5 DDR Port 3 - XXXXX - XXX -

6 EBI XXXXXXXXXXX

7 Internal Periph. X X X - X ------

Table 6-5. Internal Memory Mapping

Master

Slave

Base Address

RCBx

= 0

RCBx = 1

BMS = 1

BMS = 0

0x0000 0000 Internal ROM EBI NCS0 Internal SRAM