Datasheet

17
SAM9G45 [Summary]
6438IS–ATARM–12-Feb-13
6.2.2 Matrix Slaves
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
6.2.3 Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access
from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply not wired, and shown “-” in
the following tables.
The four DDR ports are connected differently according to the application device.
The user can disable the DDR multi-port in the DDR multi-port Register (bit DDRMP_DIS) in the Chip Configuration User
Interface.
z When the DDR multi-port is enabled (DDRMP_DIS=0), the ARM instruction and data are respectively connected
to DDR Port 0 and DDR Port 1. The other masters share DDR Port 2 and DDR Port 3.
z When the DDR multi-port is disabled (DDRMP_DIS=1), DDR Port 1 is dedicated to the LCD controller. The
remaining masters share DDR Port 2 and DDR Port 3.
Table 6-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1
Internal ROM
USB OHCI
USB EHCI
UDP High Speed RAM
LCD User Interface
Slave 2 DDR Port 0
Slave 3 DDR Port 1
Slave 4 DDR Port 2
Slave 5 DDR Port 3
Slave 6 External Bus Interface
Slave 7 Internal Peripherals