Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TFBGA 324 (15x15) 16/32-Bit 400 MHz I/O number 160

This is a summary document.

The complete document is

available on the Atmel website

at www.atmel.com.

6438IS–ATARM–12-Feb-13

Description

The ARM926EJ-S based SAM9G45 features the frequently demanded combina-

tion of user interface functionality and high data rate connectivity, including LCD

Controller, resistive touch-screen, camera interface, audio, Ethernet 10/100 and

high speed USB and SDIO. With the processor running at 400 MHz and multiple

100+ Mbps data rate peripherals, the SAM9G45 has the performance and band-

width to the network or local storage media to provide an adequate user

experience.

The SAM9G45 supports DDR2 and NAND Flash memory interfaces for program

and data storage. An internal 133 MHz multi-layer bus architecture associated with

37 DMA channels, a dual external bus interface and distributed memory including

a 64-Kbyte SRAM which can be configured as a tightly coupled memory (TCM)

sustains the high bandwidth required by the processor and the high speed

peripherals.

The I/Os support 1.8V or 3.3V operation, which are independently configurable for

the memory interface and peripheral I/Os. This feature completely eliminates the

need for any external level shifters. In addition it supports 0.8 ball pitch package for

low cost PCB manufacturing.

The SAM9G45 power management controller features efficient clock gating and a

battery backup section minimizing power consumption in active and standby

modes.

AT91SAM ARM-based Embedded MPU

SAM9G45

SUMMARY

Summary of content (53 pages)

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AT91SAM ARM-based Embedded MPU SAM9G45 SUMMARY Description The ARM926EJ-S based SAM9G45 features the frequently demanded combination of user interface functionality and high data rate connectivity, including LCD Controller, resistive touch-screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO.
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1.
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MCI0/MCI1 SD/SDIO CE ATA TWI0 TWI1 PIOE FIFO PIOD RSTC PIOA POR RTC PIOB PIOC POR VDDCORE SHDC RTT 4 GPBR RC OSC 32K PIT WDT OSC12M PLLUTMI PMC PLLA PDC DBGU AIC System Controller VDDBU NRST IN32 OUT32 SHDN WKUP IN OUT DR D DT D FI IR PCK0-PCK1 TST PIO EL JTA GS NT RS T TD I T D O TM T S C K RT CK USART0 USART1 USART2 USART3 PDC ROM 64KB SRAM 64KB 4-CH PWM I TC0 TC1 TC2 D DCache ICache MMU 32 Kbytes 32 Kbytes ITCM DTCM Bus Interface ARM926EJ-S In-Circuit Emulator
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3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Reference Voltage Comments Power Supplies VDDIOM0 DDR2 I/O Lines Power Supply Power 1.65V to 1.95V VDDIOM1 EBI I/O Lines Power Supply Power 1.65V to 1.95V or 3.0V to3.6V VDDIOP0 Peripherals I/O Lines Power Supply Power 1.65V to 3.6V VDDIOP1 Peripherals I/O Lines Power Supply Power 1.65V to 3.
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Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Reference Voltage Comments VDDBU Driven at 0V only. 0: The device is in backup mode Shutdown, Wakeup Logic SHDN Shut-Down Control Output 1: The device is running (not in backup mode). WKUP Wake-Up Input Input VDDBU Accept between 0V and VDDBU.
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Table 3-1.
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Table 3-1.
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Table 3-1.
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Table 3-1.
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Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Reference Voltage GPAD4-GPAD7 Analog Inputs Analog VDDANA TSADTRG ADC Trigger Input VDDANA TSADVREF ADC Reference Analog VDDANA Comments Notes: 1. Refer to peripheral multiplexing tables in Section 9.4 “Peripheral Signals Multiplexing on I/O Lines” for these signals. 2. When configured as an input, the NRST pin enables asynchronous reset of the device when asserted low.
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4. Package and Pinout The SAM9G45 is delivered in a 324-ball TFBGA package. 4.1 Mechanical Overview of the 324-ball TFBGA Package Figure 4-1 shows the orientation of the 324-ball TFBGA Package Figure 4-1.
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4.2 324-ball TFBGA Package Pinout Table 4-1.
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Table 4-1.
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5. Power Considerations 5.1 Power Supplies The SAM9G45 has several types of power supply pins: z VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V typical. z VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical). z VDDIOM1 pins: Power the External Bus Interface 1 I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V typical).
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6. Processor and Architecture 6.
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6.2 Bus Matrix z 12-layer Matrix, handling requests from 11 masters z Programmable Arbitration strategy z z z Fixed-priority Arbitration z Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master Burst Management z Breaking with Slot Cycle Limit Support z Undefined Burst Length Support One Address Decoder provided per Master z z z 6.2.
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6.2.2 Matrix Slaves Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed. Table 6-2. List of Bus Matrix Slaves Slave 0 Internal SRAM Internal ROM USB OHCI Slave 1 USB EHCI UDP High Speed RAM LCD User Interface 6.2.3 Slave 2 DDR Port 0 Slave 3 DDR Port 1 Slave 4 DDR Port 2 Slave 5 DDR Port 3 Slave 6 External Bus Interface Slave 7 Internal Peripherals Masters to Slaves Access All the Masters can normally access all the Slaves.
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Figure 6-1. DDR Multi-port LCD DMA DDR S1 ARM I ARM D ARM D DDRMP DIS DDR S2 MATRI DDR S3 Table 6-3. SAM9G45 Masters to Slaves Access DDRMP_DIS = 0 Master Slave 0 0 1 ARM ARM 926 Instr.
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Table 6-4. SAM9G45 Masters to Slaves Access with DDRMP_DIS = 1 (default) Master 0 ARM ARM 926 Instr. 926 Data Slave 0 1 2 3 4&5 6 7 PDC USB HOST OHCI DMA ISI DMA LCD DMA 8 9 10 11 Ethernet USB USB Host MAC Device HS EHCI Reserved Internal SRAM 0 X X X X X X - X X X - Internal ROM X X X - - - - - X - - UHP OHCI X X - - - - - - - - - UHP EHCI X X - - - - - - - - - LCD User Int.
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6.3 Peripheral DMA Controller (PDC) z Acting as one AHB Bus Matrix Master z Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. z Next Pointer support, prevents strong real-time constraints on buffer management. The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): Table 6-6. 6.
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Figure 6-2. USB Selection HS Transceiver HS Transceiver EN UDPHS 0 PA PB HS EHCI FS OHCI DMA 6.5 1 HS USB DMA DMA Controller z Two Masters z Embeds 8 channels z 64 bytes/FIFO for Channel Buffering z Linked List support with Status Write Back operation at End of Transfer z Word, HalfWord, Byte transfer support.
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6.6 Debug and Test Features z z z ARM926 Real-time In-circuit Emulator z Two real-time Watchpoint Units z Two Independent Registers: Debug Control Register and Debug Status Register z Test Access Port Accessible through JTAG Protocol z Debug Communications Channel Debug Unit z Two-pin UART z Debug Communication Channel Interrupt Handling z Chip ID Register IEEE1149.1 JTAG Boundary-scan on All Digital Pins.
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7. Memories Figure 7-1.
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7.1 Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects NCS0 to NCS5.
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z Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus. z Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters.
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z z Bootloader on a non-volatile memory z SPI DataFlash/Serial Flash connected on NPCS0 of the SPI0 z SDCard z Nand Flash z EEPROM connected on TWI0 SAM-BA Boot in case no valid program is detected in external NVM, supporting z Serial communication on a DBGU z USB Device HS Port 7.2.4.
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7.3.
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z SDRAM Power-up Initialization by Software z CAS Latency of 2, 3 Supported z Auto Precharge Command Not Used z SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported z Clock Frequency Change in Precharge Power-down Mode Not Supported 7.3.2.3 NAND Flash Error Corrected Code Controller z Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select z Single bit error correction and 2-bit Random detection.
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8. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories. 8.
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8.2 System Controller Block Diagram Figure 8-1. SAM9G45 System Controller Block Diagram System Controller VDDCORE Powered irq0-irq2 fiq periph irq 2..
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8.3 Reset Controller The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the NRST pin output.
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8.6 Slow Clock Selection The SAM9G45 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768 Hz crystal oscillator can be bypassed, by setting the bit OSC32BYP, to accept an external slow clock on XIN32. The internal RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1 respectively RCEN bit and OSC32EN bit in the system controller user interface. OSCSEL command selects the slow clock source.
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8.7 z Wait internal RC Startup Time for clock stabilization (software loop). z Switch from 32768 Hz oscillator to internal RC oscilllator by setting the bit OSCSEL to 0. z Wait 5 slow clock cycles for internal resynchronization. z Disable the 32768Hz oscillator by setting the bit OSC32EN to 0. Power Management Controller The Power Management Controller provides all the clock signals to the system.
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Figure 8-4. SAM9G45 Power Management Controller Block Diagram PLLACK USBS UHP48M USBDIV+1 USB OHCI UHP12M /4 USB EHCI /1,/2 Processor Clock Controller UPLLCK PCK int Divider MAINCK SLCK Prescaler /1,/2,/4,.../64 X /1 /1.5 /2 SysClk DDR /1 /2 MCK /3 /4 Peripherals Clock Controller ON/OFF Master Clock Controller SLCK MAINCK periph_clk[..] ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] UPLLCK Programmable Clock Controller 8.7.
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8.8 8.9 8.
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z z One 32-bit Vector Register per interrupt source z Interrupt Vector Register reads the corresponding current Interrupt Vector Protect Mode z z Fast Forcing z 8.
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9. Peripherals 9.1 Peripheral Mapping As shown in Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space. 9.2 Peripheral Identifiers Table 9-1 defines the Peripheral Identifiers of the SAM9G45.
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9.3 Peripheral Interrupts and Clock Control 9.3.1 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: z the DDR2/LPDDR Controller z the Debug Unit z the Periodic Interval Timer z the Real-Time Timer z the Real-Time Clock z the Watchdog Timer z the Reset Controller z the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 9.3.
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9.4.1 PIO Controller A Multiplexing Table 9-2.
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9.4.2 PIO Controller B Multiplexing Table 9-3.
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9.4.3 PIO Controller C Multiplexing Table 9-4.
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9.4.4 PIO Controller D Multiplexing Table 9-5.
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9.4.5 PIO Controller E Multiplexing Table 9-6.
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10. Embedded Peripherals 10.1 Serial Peripheral Interface (SPI) z z z 10.2 10.
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z RS485 with driver control signal z ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards z z IrDA modulation and demodulation z Test Modes z z 10.4 10.5 Remote Loopback, Local Loopback, Automatic Echo z Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader,...
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z z 10.8 10.
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z 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN z 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN z 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT z Single clock domain architecture z Resolution supported up to 2048 x 2048 10.12 Touch Screen Analog-to-Digital Converter (TSADC) z 8-channel ADC z Support 4-wire resistive Touch Screen z 10-bit 384 Ksamples/sec.
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z Preview scaler to generate smaller size image 10.15 8-channel DMA (DMA) z Acting as two Matrix Masters z Embeds 8 unidirectional channels with programmable priority z Address Generation z z z z Source/Destination address programming z Address increment, decrement or no change z DMA chaining support for multiple non-contiguous data blocks through use of linked lists z Scatter support for placing fields into a system memory area from a contiguous transfer.
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11. Mechanical Characteristics 11.1 Package Drawings Figure 11-1.
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12. SAM9G45 Ordering Information Table 12-1.
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Revision History In the table that follows, the initials “rfo” indicate changes requested by product experts, or made during proof reading as part of the approval process. Change Request Ref. Doc. Rev Comments 6438AS First issue Section 3. “Signal Description”, Table 3-1 in “Reset/Test” description, NRST pin updated with note concerning NRST configuration. 6600 6438BS Section 4. “Package and Pinout”, Table 4-1, updated. 6669 Introduction: 6438CS “Features” part was edited.
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Doc. Rev Comments Change Request Ref. 6438GS Section 12. “SAM9G45 Ordering Information”, fixed error in ordering information table. 7953 6438HS Section 12. “SAM9G45 Ordering Information”, a second ordering code added: AT91SAM9G45B-CU. An MRL column added too. 7979 6438IS Section 12. “SAM9G45 Ordering Information”, added AT91SAM9G45C-CU and MLR C to Table 12-1, “AT91SAM9G45 Ordering Information” 8551 Section 1. “Features”, added Write Protected Registers to “Peripherals” .
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