Datasheet

984
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
43.9.3 SSC Receive Clock Mode Register
Name: SSC_RCMR
Address: 0xF0010010
Access: Read-write
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CKS: Receive Clock Selection
• CKO: Receive Clock Output Mode Selection
• CKI: Receive Clock Inversion
0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is
shifted out on Receive Clock rising edge.
1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is
shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
• CKG: Receive Clock Gating Selection
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
– – – STOP START
76543210
CKG CKI CKO CKS
Value Name Description
0 MCK Divided Clock
1TK
TK Clock signal
2RK
RK pin
Value Name Description
0 NONE None, RK pin is an input
1 CONTINUOUS
Continuous Receive Clock, RK pin is an output
2 TRANSFER
Receive Clock only during data transfers, RK pin is an output
Value Name Description
0 CONTINUOUS None
1 EN_RF_LOW
Receive Clock enabled only if RF Pin is Low
2 EN_RF_HIGH
Receive Clock enabled only if RF Pin is High