Datasheet

980
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
43.8.1 Write Protection Registers
To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register
(US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
 “SSC Clock Mode Register” on page 983
 “SSC Receive Clock Mode Register” on page 984
 “SSC Receive Frame Mode Register” on page 986
 “SSC Transmit Clock Mode Register” on page 988
 “SSC Transmit Frame Mode Register” on page 990
 “SSC Receive Compare 0 Register” on page 996
 “SSC Receive Compare 1 Register” on page 997