Datasheet

933
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
41.7.11 Write Protected Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register
(ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR).
The protected registers are:
 “ADC Mode Register” on page 936
 “ADC Channel Sequence 1 Register” on page 938
 “ADC Channel Sequence 2 Register” on page 939
 “ADC Channel Enable Register” on page 940
 “ADC Channel Disable Register” on page 941
 “ADC Extended Mode Register” on page 950
 “ADC Compare Window Register” on page 951
 “ADC Analog Control Register” on page 953
 “ADC Touchscreen Mode Register” on page 954
 “ADC Trigger Register” on page 959