Datasheet

928
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
Figure 41-11.Touchscreen Pen Detect
The Touchscreen Pen Detect can be used to generate an ADC interrupt to wake up the system. The Pen Detect
generates two types of status, reported in the “ADC Interrupt Status Register”:
 The PEN bit is set as soon as a contact exceeds the debouncing time as defined by PENDBC and remains set
until ADC_SR is read.
 The NOPEN bit is set as soon as no current flows for a time over the debouncing time as defined by PENDBC and
remains set until ADC_SR is read.
Both bits are automatically cleared as soon as the Status Register (ADC_SR) is read, and can generate an interrupt by
writing the “ADC Interrupt Enable Register”.
Moreover, the rising of either one of them clears the other, they cannot be set at the same time.
The PENS bit of the ADC_SR indicates the current status of the pen contact.
41.7.10 Buffer Structure
The DMA read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is
repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR) the structure differs. Each data transferred to DMA
buffer, carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR
register, the 4 most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA
buffer or better checking the DMA buffer integrity.
As soon as touchscreen conversions are required, the pen detection function may help the post-processing of the buffer.
To get more details refer to Section 41.7.10.4 “Pen Detection Status”.
41.7.10.1 Classical ADC Channels Only
When no touchscreen conversion is required (i.e. TSMODE = 0 in ADC_TSMR register), the structure of data within the
buffer is defined by the ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2 registers.
If the user sequence is not used (i.e. USEQ is cleared in ADC_MR register) then only the value of ADC_CHSR register
defines the data structure. For each trigger event, enabled channels will be consecutively stored in ADC_LCDR register
and automatically transferred to the buffer.
X+/UL
X-/UR
LR
VDDANA
Y+/LL
VDDANA
GND
GND
To the ADC
VDDANA
GND
Y-/SENSE
GND
GND
Pen Interrupt
Debouncer
PENDBC
0
1
2
3
4