Datasheet

742
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
37.6.3.4 Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding
channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled
by setting the corresponding bit in the PWM_IDR register.