Datasheet

592
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
• STALL_SNT: Stall Sent
– (for Control, Bulk and Interrupt endpoints)
This bit is set by hardware after a STALL handshake has been sent as requested by the UDPHS_EPTSTAx register FRCESTALL
bit.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
• NAK_IN: NAK IN
This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host.
This bit is cleared by software.
• NAK_OUT: NAK OUT
This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
• CURBK_CTLDIR: Current Bank/Control Direction
– Current Bank (not relevant for Control endpoint):
These bits are set by hardware to indicate the number of the current bank.
Note: The current bank is updated each time the user:
- Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.
- Clears the received OUT data bit to access the next bank.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
– Control Direction (for Control endpoint only):
0 = A Control Write is requested by the Host.
1 = A Control Read is requested by the Host.
Notes: 1. This bit corresponds with the 7th bit of the bmRequestType (Byte 0 of the Setup Data).
2. This bit is updated after receiving new setup data.
• BUSY_BANK_STA: Busy Bank Number
These bits are set by hardware to indicate the number of busy banks.
IN endpoint: It indicates the number of busy banks filled by the user, ready for IN transfer.
OUT endpoint: It indicates the number of busy banks filled by OUT transaction from the Host.
Value Name Description
0 BANK0 Bank 0 (or single bank)
1 BANK1 Bank 1
2 BANK2 Bank 2
Value Name Description
0 1BUSYBANK 1 busy bank
1 2BUSYBANKS 2 busy banks
2 3BUSYBANKS 3 busy banks