Datasheet

1284
SAM9G35 [DATASHEET]
11053E–ATARM–10-Mar-2014
Note: 1. “rfo” indicates changes requested during the document review and approval loop.
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(1)
System Controller:
Figure 7-1, “SAM9G35 System Controller Block Diagram”, DDR sysclk --> DDRCK.
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ADC:
Section 41. “Analog-to-Digital Converter (ADC)” updated to show Touchscreen information.
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DMAC:
FIFO size table removed from , as the size depends on DMAC0 (see Section 31.2.1 “DMA Controller 0”) and
DMAC1 (see Section 31.2.2 “DMA Controller 1”).
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MATRIX:
Section 26.7.6.1 “EBI Chip Select Assignment Register”, description of NFD0_ON_D16 bitfield updated.
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PMC:
Section 22.2 “Embedded Characteristics”,
266 MHz DDR system clock --> 133MHz DDR system clock.
Then DDR system clock --> DDR clock.
Figure 22-2, “General Clock Block Diagram”:
- Prescaler /1,/2,/4,.../64 --> Prescaler /1,/2,/3,/4,.../64 (for Master Clock Controller).
- SysClk DDR --> 2x MCK, and connection added above with /2 block and DDRCK.
Section 22.3 “Master Clock Controller”, ...and the division by 6 --> ...and the division by 3.
Section 22.7 “LP-DDR/DDR2 Clock”, sentences with ‘ SysClk’ removed.
Section 22.13.11 “PMC Master Clock Register”:
- Value 7 for PRES field no more reserved, now with CLOCK_DIV3, Selected clock divided by 3.
- MDIV field, references to ‘SysClk DDR’ removed (x4).
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UHPHS:
Section 32.2.2 “OHCI”, Figure 32-2 “Board Schematics to Interface UHP Device Controller” added, with an
introducing sentence.
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Electrical Characteristics:
Section 46.12 “USB Transceiver Characteristics” added (extracted from SAM9G20 - 6384E: Section 41.7, Figure
41-23 and Table 41-46).
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Errata:
Section 49.1 “Boot Sequence Controller (BSC)” added as the BSC_CR register does not comply with the
programmer description.
Section 49.5 “USB High Speed Host Port (UHPHS)” removed.
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