Datasheet

699
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the char-
acter transfers.
Otherwise, the following equation determines the delay:
Delay Between Consecutive Transfers
32 DLYBCT×
MCK
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=