Datasheet

468
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
• EBISHARE: External Bus Interface is Shared
The DDR controller embedded in the EBI is used at the same time as another memory controller (SMC,..)
Reset value is 0.
0 = Only the DDR controller function is used.
1 = The DDR controller shares the EBI with another memory controller (SMC, NAND,..)
• ACTBST: ACTIVE Bank X to Burst Stop Read Access Bank Y
Reset value is 0.
0 = After an ACTIVE command in Bank X, BURST STOP command can be issued to another bank to stop current read access.
1 = After an ACTIVE command in Bank X, BURST STOP command cannot be issued to another bank to stop current read
access.
This field is unique to SDR-SDRAM, Low-power SDR-SDRAM and Low-power DDR1-SDRAM devices.
• NB: Number of Banks
The reset value is four banks.
Note: Only DDR-SDRAM 2 devices support eight internal banks.
• DECOD: Type of Decoding
The reset value is 0: sequential decoding.
0 = Sequential Decoding.
1 = Interleaved Decoding.
NB Number of banks
0 4
1 8