Datasheet

458
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
30.5.6 Write Protected Registers
To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be write-
protected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect Status
Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is automatically reset after reading the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR).
Following is a list of the write protected registers:
 “DDRSDRC Mode Register” on page 464
 “DDRSDRC Refresh Timer Register” on page 465
 “DDRSDRC Configuration Register” on page 466
 “DDRSDRC Timing Parameter 0 Register” on page 469
 “DDRSDRC Timing Parameter 1 Register” on page 471
 “DDRSDRC Timing Parameter 2 Register” on page 472
 “DDRSDRC Memory Device Register” on page 476
 “DDRSDRC High Speed Register” on page 478