Datasheet

456
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
Figure 30-24.Trp and Trcd Timings
The multi-port controller has been designed to mask these timings and thus improve the bandwidth of the system.
DDRSDRC is a multi-port controller since four masters can simultaneously reach the controller. This feature improves
the bandwidth of the system because it can detect four requests on the AHB slave inputs and thus anticipate the
commands that follow, PRECHARGE and ACTIVE commands in bank X during current access in bank Y. This allows Trp
and Trcd timings to be masked (see Figure 30-25). In the best case, all accesses are done as if the banks and rows were
already open. The best condition is met when the four masters work in different banks. In the case of four simultaneous
read accesses, when the four banks and associated rows are open, the controller reads with a continuous flow and
masks the cas latency for each different access. To allow a continuous flow, the read command must be set at 2 or 3
cycles (cas latency) before the end of current access. This requires that the scheme of arbitration changes since the
round-robin arbitration cannot be respected. If the controller anticipates a read access, and thus before the end of current
access a master with a high priority arises, then this master will not serviced.
The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the
SDRAM device at the same time.
The arbitration type is round-robin arbitration. This algorithm dispatches the requests from different masters to the
SDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the
lowest number is serviced first, then the others are serviced in a round-robin manner. To avoid burst breaking and to
provide the maximum throughput for the SDRAM device, arbitration may only take place during the following cycles:
1. Idle cycles: When no master is connected to the SDRAM device.
2. Single cycles: When a slave is currently doing a single access.
3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For bursts of defined length, pre-
dicted end of burst matches the size of the transfer. For bursts of undefined length, predicted end of burst is
generated at the end of each four beat boundary inside the INCR transfer.
4. Anticipated Access: When an anticipate read access is done while current access is not complete, the arbitration
scheme can be changed if the anticipated access is not the next access serviced by the arbitration scheme.
NOP PRCHG NOP ACT NOP READ BST NOP
0
3
Trp Trcd Latency =2
4 cycles before performing a read command
SDCLK
A[12:0]
COMMAND
BA[1:0]
DQS[1:0]
D[15:0]
DM1:0]
Da
Db