Datasheet

1150
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
PMC:
Figure 22-2 “General Clock Block Diagram”, updated the Master Clock Controller block: replaced “Prescaler
/1,/2,/4,.../64” with “Prescaler /1,/2,/3,/4,.../64”.
Section 22.3 “Master Clock Controller”, replaced “...and the division by 6” with “...and the division by 3”.
Section 22.13.11 “PMC Master Clock Register”, updated the PRES bitfield table for Value 7 which is no more
reserved: added CLOCK_DIV3 as the name and “Selected clock divided by 3” as the description.
Figure 22-2 “General Clock Block Diagram”, replaced “266 MHz DDR system clock” with “133 MHz DDR system
clock” and replaced “DDR system clock” with “DDR clock” in the corresponding note.
Figure 22-2 “General Clock Block Diagram”, replaced “SysClk DDR” with “2x MCK” and added “/2” connection to
DDRCK.
Section 22.7 “LP-DDR/DDR2 Clock”, removed phrases with references to SysClk.
Section 22.13.11 “PMC Master Clock Register”, updated as follows:
- MDIV field, removed references to SysClk DDR (x4).
Section 22.4 “Block Diagram”, removed the “/1, /2” divider block in Figure 22-2 “General Clock Block Diagram”.
Section 22.13 “Power Management Controller (PMC) User Interface”updated the CKGR_MOR reset value
(0x0100_0008 --> 0x0000_0008) in Table 22-3 “Register Mapping”.
7974
7975
8006
rfo
8401
8447
PIO:
Section 23.4.4 “Interrupt Generation”, updated the 1st paragraph.
Section 23.5.10 “Input Edge/Level Interrupt”, replaced “...to the Advanced Interrupt Controller (AIC)” with “...to
the interrupt controller” in the last phrase of the paragraph “When an input Edge or Level is detected...”.
8324
MATRIX:
Section 25.7.6.1 “EBI Chip Select Assignment Register”, updated the description and added a line to the bitfield
table in “NFD0_ON_D16: NAND Flash Databus Selection” .
8008
EBI:
Section 26.5.3.4 “Power supplies”, updated the description and added a paragraph concerning power supply
when NFD0_ON_D16=1.
Section 26.5.1 “Hardware Interface”, fixed typos in Table 26-4 “EBI Pins and External Device Connections”:
the power supply of A20, A23, A24, A25, NCS2, NCS4 and NCS5 is VDDNF and not VDDIOM.
Updated EBIx pin data in Table 26-2 “EBI Pins and Memory Controllers I/O Lines Connections” and added A13
as SDRAMC pin in the A15 line in Table 26-4 “EBI Pins and External Device Connections”.
8008
8179
rfo
PMECC:
Figure 27-2 “Software/Hardware Multibit Error Correction Dataflow”, “READ PAGE” and “PROGRAM PAGE”
positions swapped in the flow chart.
Figure 27-5 “Read Operation with Spare Decoding”, configuration revised as ”...SPAREEN set to One and AUTO
set to Zero.”
Section 27.2 “Embedded Characteristics”, added a line about supporting 8-bit Nand Flash data bus.
Section 27.6.11 “PMECC Interrupt Status Register”, replaced duplicate bits 31 - 24 with missing 7 - 0 in the
PMECC_ISR register table.
7495
8403
rfo
PMERRLOC:
Section 28.5.10 “Error Location SIGMAx Register”
, “SIGMAN” bitfield name repl
aced with “SIGMAx” in the
PMERR
LOC_SIGMAx [x=0..24] register table.
8339
Doc. Rev.
11032B Comments
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