Datasheet

1149
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
BSC:
Section 12.4.1 “Boot Sequence Configuration Register”:
- updated the BSC_CR register table
- added a reference to the “NVM Boot Sequence” section in “BOOT: Boot Media Sequence” .
Section 12.2 “Embedded Characteristics”, removed “Product-dependent order” line.
Added Section 12.3 “Product Dependencies”.
Updated the acronym of Boot Sequence Configuration Register from “BSCR” to “BSC_CR”.
7996
8184
rfo
AIC:
Section 13.10.2 “AIC Source Mode Register”, removed the PRIOR bitfield table as values 0 to 7 can be used and
updated the description of this bitfield in “PRIOR: Priority Level” .
8017
RSTC:
Section 14.5.1 “Reset Controller Control Register”, updated description of the EXTRST bitfield for the RSTC_CR
register in “EXTRST: External Reset” .
8271
RTC:
Section 15.6 “Real-time Clock (RTC) User Interface”, updated the peripheral name from “Real Time Clock” to
“Real-time Clock” and replaced the Reserved Register line “0x30-0xF8” with two lines “0x30–0xC4” and “0xC8–
0xF8” (Reserved Register) in Table 15-1 “Register Mapping”.
8280
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WDT:
Added the 4th paragraph “If the watchdog is restarted...” in Section 17.4 “Functional Description”.
Section 17.5.3 “Watchdog Timer Status Register”, added a note in “WDERR: Watchdog Error” .
Updated Section 17.2 “Embedded Characteristics”.
8128:
8218
SHDWC:
Removed AMBA references from Section 18.2 “Embedded Characteristics”.
Section 18.3 “Block Diagram”, removed redundant Figure 18-2. Sutdown Controller Block Diagram.
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8454
GPBR:
Section 19.3.1 “General Purpose Backup Register x”, removed ‘x’ from the bitfield names in the SYS_GPBRx
register table and in the description below.
7990
SCKC:
Section 20.3 “Block Diagram”, updated the first paragraph: the RCEN, OSC32EN, OSCSEL and OSC32BYP bits
are located not in Slow Clock Control Register (SCKCR) but in Slow Clock Configuration Register (SCKC_CR).
Fixed Figure 20-1 “Block Diagram” for better representation.
8322
rfo
CKGR:
Section 21.6.2 “Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal”, fixed a typo in the sequence
order: MAINRDY --> MOSCXTS
.
Section 21.7 “Divider and PLLA Block”, added the PLLADIV2 block between the PLLA block and the PLLACK
reference in Figure 21-6 “Divider and PLLA Block Diagram”.
Updated Crystal Oscillator range from “3 to 20 MHz” to “12 to 16 MHz” in Section 21.2 “Embedded
Characteristics”, Section 21.5 “Main Clock”, Figure 21-3 “Main Clock Block Diagram”, Section 21.6.6 “12 to 16
MHz Crystal Oscillator”, Section 21.6.7 “Main Clock Oscillator Selection”, and Section 21.6.8 “Main Clock
Frequency Counter”.
Section 21.3 “CKGR Block Diagram”, updated the UPLL block connections in Section 21-1 “Clock Generator
Block Diagram”.
8327
8401
8413
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