Datasheet

1147
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
Section 46. “Electrical Characteristics”
Table 46-2 “DC Characteristics”: added input impedance characteristics
Table 46-5 “Processor Clock Waveform Parameters”: added footnote “For DDR2 usage only, there are no limitations to LP-
DDR, SDRAM and mobile SDRAM”
Figure 46-2 “Main Oscillator Schematics”: added note “A 1K resistor must be added on XOUT pin for crystals with
frequencies lower than 8 MHz” below figure
Table 46-10 “12 MHz RC Oscillator Characteristics”: added conditions to parameter “Power Consumption Oscillation”
Table 46-18 “I/O Characteristics”: added values; replaced “40 pF” with “20 pF” in footnote defining 3.3V domain
Revised Section 46.14 “POR Characteristics” to add Figure 46-5 “General Presentation of POR Behavior” and Section
46.14.2 “Backup Power Supply POR Characteristics”
Table 46-28 “Core Power Supply POR Characteristics”: added conditions to parameter “Threshold Voltage Falling”
Promoted Section 46.15 “Power Sequence Requirements” to heading level 2 (was level 3)
Table 46-31 “Zero Hold Mode Use Maximum System Clock Frequency (MCK)”: in values columns, changed header “Min”
to “Max”
Added Section 46.18.5.4 “RMII Mode”
Added Section 46.19 “Two-wire Interface Characteristics”
Section 49. “SAM9G25 Errata”
Updated Section 49.2.1 “RSTC: Reset during SDRAM Accesses”
Added Section 49.6 “Boot Strategy”
Added Section 49.7 “Real Time Clock (RTC)”
Doc. Rev.
11032C Comments
Change
Request
Ref.
(1)
Introduction:
Section 1. “Features”, added DBGU in the Peripherals list.
Section 8.2 “Peripheral Identifiers”, added data on System Controller Interrupt in Table 8-1 “Peripheral
Identifiers”.
Replaced ‘247-ball BGA’ with ‘247-ball TFBGA’ and added 247-ball VFBGA package references in:
- “Description”
- Section 1. “Features”
- Section “”, including:
- Section 4.2 “Overview of the 247-ball BGA Packages”
- Section 4.2.1 “247-ball TFBGA Package”
- Section 4.2.2 “247-ball VFBGA Package”
- Section 4.5 “247-ball BGA Package Pinout”
Fixed typos in Table 4-3 “Pin Description BGA217” (balls A1, B1; signals D16-D31) and Table 4-4 “Pin
Description BGA247” (balls A2, C5, P17, U15, J10, E10; signals AD0-AD4, D16-D31).
rfo
8516
8593
8579,
8604
MATRIX:
Section 25.7.6.1 “EBI Chip Select Assignment Register”, updated the description of a warning note in
“DDR_MP_EN: DDR Multi-port Enable” .
8532
DMAC:
Added Section 31.2.1 “DMA Controller 0” and Section 31.2.2 “DMA Controller 1”.8526
Doc. Rev.
11032D Comments