Datasheet

974
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
44.5.11 ISI Status Register
Name: ISI_SR
Address: 0xF8048028
Access: Read-only
Reset: 0x00000000
• ENABLE (this bit is a status bit)
0: Module is disabled.
1: Module is enabled.
• DIS_DONE: Module Disable Request has Terminated
1: Disable request has completed. This flag is reset after a read operation.
• SRST: Module Software Reset Request has Terminated
1: Software reset request has completed. This flag is reset after a read operation.
• CDC_PND: Pending Codec Request (this bit is a status bit)
0: Indicates that no Codec request is pending.
1: Indicates that the request has been taken into account but cannot be serviced within the current frame. The operation is post-
poned to the next frame.
• VSYNC: Vertical Synchronization
1: Indicates that a Vertical synchronization has been detected since the last read of the status register.
• PXFR_DONE: Preview DMA Transfer has Terminated.
When set to one, this bit indicates that the DATA transfer on the preview channel has completed. This flag is reset after a read
operation.
• CXFR_DONE: Codec DMA Transfer has Terminated.
When set to one, this bit indicates that the DATA transfer on the codec channel has completed. This flag is reset after a read
operation.
• SIP: Synchronization in Progress (this is a status bit)
When the status of the preview or codec DMA channel is modified, a minimum amount of time is required to perform the clock
domain synchronization. This bit is set when this operation occurs. No modification of the channel status is allowed when this bit
is set, to guarantee data integrity.
31 30 29 28 27 26 25 24
––––FR_OVRCRC_ERR C_OVR P_OVR
23 22 21 20 19 18 17 16
––––SIP–CXFR_DONEPXFR_DONE
15 14 13 12 11 10 9 8
–––––VSYNC–CDC_PND
76543210
–––––SRSTDIS_DONEENABLE