Datasheet

563
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
32.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint)
Name: UDPHS_EPTSETSTAx [x=0..6] (ISOENDPT)
Address: 0xF803C114 [0], 0xF803C134 [1], 0xF803C154 [2], 0xF803C174 [3], 0xF803C194 [4], 0xF803C1B4 [5],
0xF803C1D4 [6]
Access: Write-only
This register view is relevant only if EPT_TYPE=0x1 in “UDPHS Endpoint Configuration Register” on page 546
For additional Information, see “UDPHS Endpoint Status Register (Isochronous Endpoint)” on page 570.
• RXRDY_TXKL: KILL Bank Set (for IN Endpoint)
0 = No effect.
1 = Kill the last written bank.
• TXRDY_TRER: TX Packet Ready Set
0 = No effect.
1 = Set this bit after a packet has been written into the endpoint FIFO for IN data transfers
– This flag is used to generate a Data IN transaction (device to host).
– Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY_TRER is cleared.
– Transfer to the FIFO is done by writing in the “Buffer Address” register.
– Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting
TXRDY_TRER to one.
– UDPHS bus transactions can start.
– TXCOMP is set once the data payload has been sent.
– Data should be written into the endpoint FIFO only after this bit has been cleared.
– Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
––––TXRDY_TRER–RXRDY_TXKL–
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