Datasheet

472
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
Buffer Transfer Completed Interrupt, or poll for the Channel Enable. (DMAC_CHSR.ENAx) bit until it is cleared by
hardware, to detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 31-3 on page
462, the following step is performed.
19. The DMAC fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, and
automatically reprograms the DMAC_DADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel
registers. Note that the DMAC_SADDRx is not re-programmed as the reloaded value is used for the next DMAC
buffer transfer. If the next buffer is the last buffer of the DMAC transfer, then the DMAC_CTRLBx and
DMAC_DSCRx registers just fetched from the LLI should match Row 1 of Table 31-3 on page 462. The DMAC
transfer might look like that shown in Figure 31-11 on page 472.
Figure 31-11.Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address
The DMAC Transfer flow is shown in Figure 31-12 on page 473.
Address of
Source Layer
Address of
Destination Layer
Source Buffers
Destination Buffers
SADDR
Buffer0
Buffer1
Buffer2
BufferN
DADDR(N)
DADDR(1)
DADDR(0)
DADDR(2)