Datasheet

310
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
At reset the selected current drive is LOW.
To improve EMI, programmable delay has been inserted on lines able to run at high speed. The control of these delays is
as follows:
z EBI (DDR2SDRC\SMC\NAND Flash)
D[15:0] controlled by 2 registers DELAY1 and DELAY2 located in the SMC user interface.
z D[0] <=> DELAY1[3:0],
z D[1] <=> DELAY1[7:4],...,
z D[6] <=> DELAY1[27:24],
z D[7] <=> DELAY1[31:28]
z D[8] <=> DELAY2[3:0],
z D[9] <=> DELAY2[7:4],...,
z D[14] <=> DELAY2[27:24],
z D[15] <=> DELAY2[31:28]
D[31:16] on PIOD[21:6] controlled by 2 registers, DELAY3 and DELAY4 located in the SMC user interface.
z D[16] <=> DELAY3[3:0],
z D[17] <=> DELAY3[7:4],...,
z ...
z D[24] <=> DELAY4[3:0]
z D[25] <=> DELAY4[7:4]
(1)
z D[26] <=> DELAY4[11:8]
(1)
z D[27] <=> DELAY4[15:12]
(1)
z D[28] <=> DELAY4[19:16]
(1)
z D[29] <=> DELAY4[23:20]
z D[30] <=> DELAY4[27:24]
z D[31] <=> DELAY4[31:28]
Note: 1. A20, A23, A24 and A25 are multiplexed with D25, D26, D27 and D28 in PIOD, on PD15, PD16, PD17 and
PD18 lines respectively. Delays applied on these IO lines are common to A20, A23, A24, A25 and D25,
D26, D27, D28 respectively.
A[25:0], controlled by 4 registers DELAY5, DELAY6, DELAY7 and DELAY8 located in the SMC user interface.
z A[0] <=> DELAY5[3:0]
z A[1] <=> DELAY5[7:4],...,
z ...
z A[14] <=> DELAY6[27:24]
z A[15] <=> DELAY6[31:28]
z A[16] <=> DELAY7[3:0]
z A[17] <=> DELAY7[7:4]
z A[18] <=> DELAY7[11:8]
and
z A19 <=> DELAY7[15:12]
z A21 <=> PD[2] <=> DELAY7[23:20]
z A22 <=> PD[3] <=> DELAY7[27:24]