Datasheet

1088
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
EBI:
Section 26.5.3.4 “Power supplies”, updated the description and added a paragraph concerning power supply
when NFD0_ON_D16=1.
Section 26.5.1 “Hardware Interface”, fixed typos in Table 26-4 “EBI Pins and External Device Connections”:
the power supply of A20, A23, A24, A25, NCS2, NCS4 and NCS5 is VDDNF and not VDDIOM.
Updated EBIx pin data in Table 26-2 “EBI Pins and Memory Controllers I/O Lines Connections” and added A13
as SDRAMC pin in the A15 line in Table 26-4 “EBI Pins and External Device Connections”.
8008
8179
rfo
PMECC:
Figure 27-2 “Software/Hardware Multibit Error Correction Dataflow”, “READ PAGE” and “PROGRAM PAGE”
positions swapped in the flow chart.
Figure 27-5 “Read Operation with Spare Decoding”, configuration revised as ”...SPAREEN set to One and AUTO
set to Zero.”
Section 27.2 “Embedded Characteristics”, added a line about supporting 8-bit Nand Flash data bus.
Section 27.6.11 “PMECC Interrupt Status Register”, replaced duplicate bits 31 - 24 with missing 7 - 0 in the
PMECC_ISR register table.
7495
8403
rfo
PMERRLOC:
Section 28.5.10 “Error Location SIGMAx Register”, “SIGMAN” bitfield name replaced with “SIGMAx” in the
PMERRLOC_SIGMAx [x=0..24] register table.
8339
SMC:
Replaced “...turned out...” with “...switched to output mode...” in the first paragraphes in Section 29.9.4.1 “Write is
Controlled by NWE (WRITE_MODE = 1)”
and Section 29.9.4.2 “Write is Controlled by NCS (WRITE_MODE =
0)”
.
7925
DDRSDRC:
Section 30.2 “Embedded Characteristics”, removed duplicate reference to DDR2-SDRAM. 8146
DMAC:
Section 31.4.5.1 “Programming Examples”, value ‘1’ --> ‘0’ for a masked BTC (DMAC_EBCIMR.BTCx = ‘0’) in
“Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4)”.
Updated names:
- ‘Buffer Complete Interrupt’ --> ‘Buffer Transfer Completed Interrupt’
- ‘Chained Buffer Interrupt’ --> ‘Chained Buffer Transfer Completed Interrupt’
- ‘Transfer Complete Interrupt’ --> ‘Chained Buffer Transfer Completed Interrupt’
- KEEPON[n] --> KEEPx, STALLED[n] --> STALx, ENABLE[n] --> ENAx, SUSPEND[n] --> SUSPx, RESUME[n] -
-> RESx, EMPTY[n] --> EMPTx.
- Read the Channel Enable register --> Read the Channel Handler Status register.
Detailed bitfield acronyms when missing.
FIFO size table removed from Section 31.1 “Description”.
Updated Section 31.2 “Embedded Characteristics”:
- updated the list of embedded characteristics
- removed Section 31.2.1 DMA Controller 0 and Section 31.2.1 DMA Controller 1
Section 31.7.16 “DMAC Channel x [x = 0..7] Control A Register”, updated SCSIZE and DCSIZE bitfield tables.
Section 31.7.21 “DMAC Write Protect Mode Register”, updated the descriptions of WPEN and WPKEY bitfields:
replaced the wrong values 0x444D4143 and 0x50494F with 0x444D41, and replaced ‘(“DMAC” in ASCII)’ with
‘(“DMA” in ASCII)’.
7393
8004
rfo
8143
8404
Doc. Rev.
11032B
Comments Change
Request
Ref.