Datasheet

1087
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
SHDWC:
Removed AMBA references from Section 18.2 “Embedded Characteristics”.
Section 18.3 “Block Diagram”, removed redundant Figure 18-2. Sutdown Controller Block Diagram.
rfo
8454
GPBR:
Section 19.3.1 “General Purpose Backup Register x”, removed ‘x’ from the bitfield names in the SYS_GPBRx
register table and in the description below.
7990
SCKC:
Section 20.3 “Block Diagram”, updated the first paragraph: the RCEN, OSC32EN, OSCSEL and OSC32BYP bits
are located not in Slow Clock Control Register (SCKCR) but in Slow Clock Configuration Register (SCKC_CR).
Fixed Figure 20-1 “Block Diagram” for better representation.
8322
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CKGR:
Section 21.6.2 “Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal”, fixed a typo in the sequence
order: MAINRDY --> MOSCXTS
.
Section 21.7 “Divider and PLLA Block”, added the PLLADIV2 block between the PLLA block and the PLLACK
reference in Figure 21-6 “Divider and PLLA Block Diagram”.
Updated Crystal Oscillator range from “3 to 20 MHz” to “12 to 16 MHz” in Section 21.2 “Embedded
Characteristics”, Section 21.5 “Main Clock”, Figure 21-3 “Main Clock Block Diagram”, Section 21.6.6 “12 to 16
MHz Crystal Oscillator”, Section 21.6.7 “Main Clock Oscillator Selection”, and Section 21.6.8 “Main Clock
Frequency Counter”.
Section 21.3 “CKGR Block Diagram”, updated the UPLL block connections in Section 21-1 “Clock Generator
Block Diagram”.
8327
8401
8413
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PMC:
Figure 22-2 “General Clock Block Diagram”, updated the Master Clock Controller block: replaced “Prescaler
/1,/2,/4,.../64” with “Prescaler /1,/2,/3,/4,.../64”.
Section 22.3 “Master Clock Controller”, replaced “...and the division by 6” with “...and the division by 3”.
Section 22.13.11 “PMC Master Clock Register”, updated the PRES bitfield table for Value 7 which is no more
reserved: added CLOCK_DIV3 as the name and “Selected clock divided by 3” as the description.
Figure 22-2 “General Clock Block Diagram”, replaced “266 MHz DDR system clock” with “133 MHz DDR system
clock” and replaced “DDR system clock” with “DDR clock” in the corresponding note.
Figure 22-2 “General Clock Block Diagram”, replaced “SysClk DDR” with “2x MCK” and added “/2” connection to
DDRCK.
Section 22.7 “LP-DDR/DDR2 Clock”, removed phrases with references to SysClk.
Section 22.13.11 “PMC Master Clock Register”, updated as follows:
- MDIV field, removed references to SysClk DDR (x4).
Section 22.4 “Block Diagram”, removed the “/1, /2” divider block in Figure 22-2 “General Clock Block Diagram”.
Section 22.13 “Power Management Controller (PMC) User Interface”updated the CKGR_MOR reset value
(0x0100_0008 --> 0x0000_0008) in Table 22-3 “Register Mapping”.
7974
7975
8006
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8401
8447
PIO:
Section 23.4.4 “Interrupt Generation”, updated the 1st paragraph.
Section 23.5.10 “Input Edge/Level Interrupt”, replaced “...to the Advanced Interrupt Controller (AIC)” with “...to
the interrupt controller” in the last phrase of the paragraph “When an input Edge or Level is detected...”.
8324
MATRIX:
Section 25.7.6.1 “EBI Chip Select Assignment Register”, updated the description and added a line to the bitfield
table in “NFD0_ON_D16: NAND Flash Databus Selection”.
8008
Doc. Rev.
11032B
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