Datasheet

1069
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or
5 or 7 (Receive Start Selection), two Periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the
TK (or RK) edge and the signal change. The Max access time is the time between the TK edge and the signal stabili-
zation. Figure 46-20 illustrates Min and Max accesses for SSC0. The same applies to SSC1, SSC4, and SSC7,
SSC10 and SSC13.
3. 1.8V domain: V
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 20pF.
4. 3.3V domain: V
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 30pF.
Figure 46-20.Min and Max access time of output signals
46.17.3 ISI
46.17.3.1 Timing conditions
Timings are given assuming capacitance loads on
Table 46-39.
SSC
11
RF/RD setup time before RK edge (RK output)
1.8V domain
(3)
3.3V domain
(4)
14.1 - t
CPMCK
10.0 - t
CPMCK
ns
SSC
12
RF/RD hold time after RK edge (RK output)
1.8V domain
(3)
3.3V domain
(4)
t
CPMCK
- 2.5
t
CPMCK
- 1.8
ns
SSC
13
RK edge to RF (RK output)
1.8V domain
(3)
3.3V domain
(4)
-5.9
-4.9
5.2
4.3
ns
Table 46-38. SSC Timings (Continued)
Symbol Parameter Cond Min Max Units
TK (CKI =0)
TF/TD
SSC
0min
TK (CKI =1)
SSC
0max
Table 46-39. Capacitance Load
Corner
Supply MAX STH MIN
3.3V 30pf 30pf 0 pf
1.8V 20pf 20pf 0 pF