Datasheet

1057
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
46.15 SMC Timings
46.15.1 Timing Conditions
SMC Timings are given for MAX corners.
Timings are given assuming a capacitance load on data, control and address pads:
In the following tables, t
CPMCK
is MCK period.
46.15.2 Timing Extraction
46.15.2.1Zero Hold Mode Restrictions
46.15.2.2Read Timings
Table 46-28. Capacitance Load
Corner
Supply MAX MIN
3.3V 50pF 5 pF
1.8V 30 pF 5 pF
Table 46-29. Zero Hold Mode Use Maximum system clock frequency (MCK)
Symbol Parameter Min Units
VDDIOM supply 1.8V 3.3V
Zero Hold Mode Use
Fmax MCK frequency 66 66 MHz
Table 46-30. SMC Read Signals - NRD Controlled (READ_MODE= 1)
Symbol Parameter Min Units
VDDIOM supply 1.8V 3.3V
NO HOLD SETTINGS (nrd hold = 0)
SMC
1
Data Setup before NRD High 13.6 11.7 ns
SMC
2
Data Hold after NRD High 0 0 ns
HOLD SETTINGS (nrd hold ≠ 0)
SMC
3
Data Setup before NRD High 10.9 9.0 ns
SMC
4
Data Hold after NRD High 0 0 ns
HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold =0)
SMC
5
NBS0/A0, NBS1, NBS2/A1, NBS3, A2 -
A25 Valid before NRD High
(nrd setup + nrd pulse)* t
CPMCK
-
4.7
(nrd setup + nrd pulse)*
t
CPMCK
- 4.7
ns
SMC
6
NCS low before NRD High
(nrd setup + nrd pulse - ncs rd
setup) * t
CPMCK
- 4.3
(nrd setup + nrd pulse -
ncs rd setup) * t
CPMCK
- 4.4
ns
SMC
7
NRD Pulse Width nrd pulse * t
CPMCK
- 3.2 nrd pulse * t
CPMCK
- 3.3 ns