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11032C–ATARM–25-Jan-13

Description

Based on the ARM926EJ-S™ core, the SAM9G25 is an embedded microprocessor

unit, running at 400 MHz and featuring connectivity peripherals, a high data bandwidth

architecture and a small footprint package option, making it an optimized solution for

industrial applications.

The multi-layer bus matrix is linked to 2 x 8 DMA channels as well as DMAs dedicated

to the communication and interface peripherals, ensuring uninterrupted data transfers

with minimal processor overhead. Interface peripherals include a camera interface that

supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and

up to 12-bit grayscale sensors. Communication peripherals include a soft modem

supporting exclusively the Conexant SmartDAA line driver, HS (480 Mbps) USB Host

and Device ports with on-chip transceivers, FS USB Host, 10/100 Ethernet MAC, two

HS SDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S, multiple TWIs and 10-bit ADC.

The External Bus Interface incorporates controllers offering support for 4-bank and 8-

bank DDR2/LPDDR, SDRAM/LPSDRAM, static memories, as well as specific circuitry

for MLC/SLC NAND Flash with integrated ECC up to 24 bits.

The SAM9G25 is available in a 217-ball BGA package with 0.8 mm ball pitch, as well

as in 247-ball TFBGA and 247-ball VFBGA packages with 0.5 mm ball pitch, making it

ideally suited for space-constrained applications.

AT91SAM ARM-based Embbedded MPU

SAM9G25

DATASHEET

Summary of content (1102 pages)

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AT91SAM ARM-based Embbedded MPU SAM9G25 DATASHEET Description Based on the ARM926EJ-S™ core, the SAM9G25 is an embedded microprocessor unit, running at 400 MHz and featuring connectivity peripherals, a high data bandwidth architecture and a small footprint package option, making it an optimized solution for industrial applications.
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1. Features z z z z z Core z ARM926EJ-S™ ARM® Thumb® Processor running at up to 400 MHz @ 1.0V +/- 10% z 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit Memories z One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, SDCard, DataFlash® or serial DataFlash. Programmable order.
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z z z One 12-channel 10-bit Analog-to-Digital Converter z Soft Modem z Write Protected Registers I/O z Four 32-bit Parallel Input/Output Controllers z 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os z Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input z Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output Packages z 217-ball BGA, pitch 0.8 mm z 247-ball TFBGA, pitch 0.
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Block Diagram PC T TS 1 CK -P K0 FIQ IRQ XD DR D X DT System Controller AIC DBGU RSTC RTC RC 4 GPBR WDT PIT PLLA PLLUTMI PMC OSC12M 12M RC OSC 32K POR SHDC PIOC PIOD POR PIOB MMU D DCache 16 KB I Bus Interface ROM 32 KB + 96 KB ICache 16 KB ARM926EJ-S In-Circuit Emulator JTAG / Boundary Scan JT AG S Peripheral Bridge FS Transc. HS Transc.
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3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1.
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Table 3-1.
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Table 3-1.
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Table 3-1.
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4. Package and Pinout The SAM9G25 is available in 217-ball BGA, 247-ball TFBGA and 247-ball VFBGA packages. 4.1 Overview of the 217-ball BGA Package Figure 4-1 shows the orientation of the 217-ball BGA Package. Figure 4-1.
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4.2 Overview of the 247-ball BGA Packages The SAM9G25 is available in the following 247-ball BGA packages: 4.2.1 z 247-ball TFBGA z 247-ball VFBGA 247-ball TFBGA Package Figure 4-2 shows orientation of the 247-ball TFBGA package. Figure 4-2. Orientation of the 247-ball TFBGA Package BOTTOM VIEW BALL A1 4.2.2 247-ball VFBGA Package Please refer to Section 4.2.1 “247-ball TFBGA Package”.
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4.3 I/O Description Table 4-1. SAM9G25 I/O Type Description I/O Type Voltage Range GPIO Analog Pull-up Pull-down Schmitt Trigger 1.65-3.6V Switchable Switchable Switchable GPIO_CLK 1.65-3.6V Switchable Switchable Switchable GPIO_CLK2 1.65-3.6V Switchable Switchable Switchable GPIO_ANA 3.0-3.6V EBI 1.65-1.95V, 3.03.6V Switchable Switchable EBI_O 1.65-1.95V, 3.03.6V Reset State Reset State EBI_CLK 1.65-1.95V, 3.03.6V I Switchable Switchable RSTJTAG 3.0-3.
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Table 4-2. 4.3.1 SAM9G25 I/O Type Assignment and Frequency (Continued) I/O Type I/O Frequency (MHz) Charge Load (pF) Output Current USBHS 480 10 HHSDPA, HHSDPB/DHSDP, HHSDMA, HHSDMB/DHSDM CLOCK 50 50 XIN, XOUT, XIN32, XOUT32 DIB 25 25 DIBN, DIBP Signal Name Reset State In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics. z “PIO” “/” signal Indicates whether the PIO Line resets in I/O mode or in peripheral mode.
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4.4 217-ball BGA Package Pinout Table 4-3.
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Table 4-3.
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Table 4-3.
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Table 4-3.
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Table 4-3.
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Table 4-3.
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4.5 247-ball BGA Package Pinout Table 4-4 provides the pin description of 247-ball TFBGA and 247-ball VFBGA packages. Table 4-4.
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Table 4-4.
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Table 4-4.
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Table 4-4.
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Table 4-4.
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Table 4-4.
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Table 4-4.
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5. Power Considerations 5.1 Power Supplies The SAM9G25 has several types of power supply pins. Table 5-1. SAM9G25 Power Supplies Name Voltage Range, nominal Powers VDDCORE 0.9-1.1V, 1.0V ARM core, internal memories, internal peripherals and part of the system controller. GNDCORE External Memory Interface I/O lines GNDIOM 3.0-3.6V, 3.3V NAND Flash I/O and control, D16-D32 and multiplexed SMC lines GNDIOM VDDIOP0 1.65-3.6V A part of Peripheral I/O lines(1) GNDIOP VDDIOP1 1.65-3.
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6. Memories Figure 6-1.
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6.1 Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. Banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects, EBI_NCS0 to EBI_NCS5.
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6.3.
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7. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories.
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Figure 7-1. SAM9G25 System Controller Block Diagram System Controller VDDCORE Powered irq fiq periph_irq[2..
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7.1 7.2 Chip Identification z Chip ID: 0x819A_05A1 z Chip ID Extension: 3 z JTAG ID: 0x05B2_F03F z ARM926 TAP ID: 0x0792_603F Backup Section The SAM9G25 features a Backup Section that embeds: z RC Oscillator z Slow Clock Oscillator z Real Time Counter (RTC) z Shutdown Controller z 4 Backup Registers z Slow Clock Control Register (SCKCR) z Boot Sequence Configuration Register (BSCR) z A part of the Reset Controller (RSTC) This section is powered by the VDDBU rail.
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8. Peripherals 8.1 Peripheral Mapping As shown in Figure 6-1, the Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xF000_0000 and 0xFFFF_C000. Each User Peripheral is allocated 16 Kbytes of address space. 8.2 Peripheral Identifiers Table 8-1 defines the Peripheral Identifiers of the SAM9G25.
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Table 8-1. 8.
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9. ARM926EJ-S™ 9.1 Description The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density.
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z z z z z Write Buffer z 16-word Data Buffer z 4-address Address Buffer z Software Control Drain DCache Write-back Buffer z 8 Data Word Entries z One Address Entry z Software Control Drain Memory Management Unit (MMU) z Access Permission for Sections z Access Permission for Large Pages and Small Pages z 16 Embedded Domains z 64 Entry Instruction TLB and 64 Entry Data TLB Memory Access z 8-bit, 16-bit, and 32-bit Data Types z Separate AMBA AHB Buses for Both the 32-bit Data Interf
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9.3 Block Diagram Figure 9-1.
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9.4 ARM9EJ-S Processor 9.4.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: z ARM state: 32-bit, word-aligned ARM instructions. z THUMB state: 16-bit, halfword-aligned Thumb instructions. z Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 9.4.
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9.4.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: z User mode is the usual ARM program execution state. It is used for executing most application programs z Fast Interrupt (FIQ) mode is used for handling fast interrupts.
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The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed.
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Figure 9-2 shows the status register format, where: z N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags z The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR.
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The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR.
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Table 9-2. Mnemonic BX LDR Operation Mnemonic Operation Branch and Exchange SWI Software Interrupt Load Word STR Store Word LDRSH Load Signed Halfword LDRSB Load Signed Byte LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRBT 9.4.
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9.4.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: z Branch instructions z Data processing instructions z Load and Store instructions z Load and Store multiple instructions z Exception-generating instruction For further details, see the ARM Technical Reference Manual. Table 9-4 gives the Thumb instruction mnemonic list. Table 9-4.
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9.5 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: z ARM9EJ-S z Caches (ICache, DCache and write buffer) z TCM z MMU z Other system options To control these features, CP15 provides 16 additional registers. See Table 9-5. Table 9-5.
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9.5.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: z MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. z MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
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9.6 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS, WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13.
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9.6.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access.
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On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 9.7.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. 9.7.2.1 DCache The DCache needs the MMU to be enabled.
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9.8 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: 9.8.
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10. 10.1 Debug and Test Description The SAM9G25 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel.
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Block Diagram Figure 10-1. Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP Boundary Port JTAGSEL TDO RTCK POR Reset and Test ARM9EJ-S TST ICE-RT ARM926EJ-S DMA DBGU PIO 10.
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10.4 Application Examples 10.4.1 Debug Environment Figure 10-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 10-2.
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10.4.2 Test Environment Figure 10-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 10-3.
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10.5 Debug and Test Pin Description Table 10-1.
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10.6 Functional Description 10.6.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 10.6.2 EmbeddedICE™ The ARM9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface.
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A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The device Debug Unit Chip ID value is 0x819A_05A1 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 10.6.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high.
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10.6.6 JTAG ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B2F • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_F03F.
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11. Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed thanks to the BMS pin. This allows the user to layout the ROM or an external memory to 0x0. The sampling of the BMS pin is done at reset. If BMS is detected at 0, the controller boots on the memory connected to Chip Select 0 of the External Bus Interface.
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11.3 Chip Setup At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz Fast RC Oscillator. Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode. 2. Main Oscillator Detection: the Main Clock is switched to the 32 kHz RC oscillator to allow external clock frequency to be measured. Then the Main Oscillator is enabled and set in bypass mode.
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Table 11-2. Boot Sequence Configuration Register Values BOOT Value SPI0 NPCS0 SDCard NAND Flash SPI0 NPCS1 TWI EEPROM SAM-BA Monitor 5 - - - - - Y 6 - - - - - Y 7 - - - - - Y Figure 11-2.
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11.4.2 NVM Bootloader Program Description Figure 11-3. NVM Bootloader Program Diagram Start Initialize NVM Initialization OK ? No Restore the reset values for the peripherals and Jump to next boot solution Yes Valid code detection in NVM NVM contains valid code No Yes Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals.
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Figure 11-4. Remap Action after Download Completion 0x0000_0000 0x0000_0000 REMAP Internal ROM Internal SRAM 0x0010_0000 0x0010_0000 Internal ROM Internal ROM 0x0030_0000 0x0030_0000 Internal SRAM Internal SRAM 11.4.3 Valid Code Detection There are two kinds of valid code detection. 11.4.3.1 ARM Exception Vectors Check The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven ARM exception vectors.
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Figure 11-7. Structure of the ARM Vector 6 31 0 Size of the code to download in bytes The value has to be smaller than 24 kbytes. This size is the internal SRAM size minus the stack size used by the ROM Code at the end of the internal SRAM. Example An example of valid vectors follows: 00 ea000006 04 eafffffe 08 ea00002f 0c eafffffe 10 eafffffe 14 00001234 18 eafffffe B0x20 B0x04 B_main B0x0c B0x10 B0x14<- Code size = 4660 bytes B0x18 11.4.3.2 boot.
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Figure 11-8. Boot NAND Flash Download Start Initialize NAND Flash interface Send Reset command No First page contains valid header Yes No NAND Flash is ONFI Compliant Yes Read NAND Flash and PMECC parameters from the header Read NAND Flash and PMECC parameters from the ONFI Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals.
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NAND Flash Specific Header Detection This is the first method used to determine NAND Flash parameters. After Initialization and Reset command, the Boot Program reads the first page without ECC check, to determine if the NAND parameter header is present. The header is made of 52 times the same 32-bit word (for redundancy reasons) which must contain NAND and PMECC parameters used to correctly perform the read of the rest of the data in the NAND.
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ONFI 2.2 Parameters In case no valid header has been found, the Boot Program will check if the NAND Flash is ONFI compliant, sending a Read Id command (0x90) with 0x20 as parameter for the address.
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unsigned unsigned unsigned unsigned unsigned int int int int int nandWR; spareEna; modeAuto; clkCtrl; interrupt; int tt; int mm; int nn; short *alpha_to; short *index_of; short partialSyn[100]; short si[100]; /* sigma table */ short smu[TT_MAX + 2][2 * TT_MAX + 1]; /* polynom order */ short lmu[TT_MAX + 1]; } PMECC_paramDesc_struct; The Galois field tables are mapped in the ROM just after the ROM code, as described in Figure 11-9 below: Figure 11-9.
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11.4.4.3 SD Card Boot The SD Card bootloader uses MCI0. It looks for a “boot.bin” file in the root directory of a FAT12/16/32 formatted SD Card. Supported SD Card Devices SD Card Boot supports all SD Card memories compliant with SD Memory Card Specification V2.0. This includes SDHC cards. 11.4.4.4 SPI Flash Boot Two kinds of SPI Flash are supported: SPI Serial Flash and SPI DataFlash.
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Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state.
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11.5 SAM-BA Monitor If no valid code has been found in NVM during the NVM bootloader sequence, the SAM-BA Monitor program is launched. The SAM-BA Monitor principle is to: z Initialize DBGU and USB z Check if USB Device enumeration has occurred z Check if characters have been received on the DBGU Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in Table 11-4. Figure 11-10.
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z z z z Note: z z z Mode commands: z Normal mode configures SAM-BA Monitor to send / receive data in binary format, z Terminal mode configures SAM-BA Monitor to send / receive data in ascii format. Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. z Address: Address in hexadecimal. z Value: Byte, halfword or word to write in hexadecimal. z Output: ‘>’ Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. z Address: Address in hexadecimal.
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Figure 11-11 shows a transmission using this protocol. Figure 11-11.Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 11.5.3 USB Device Port 11.5.3.1 Supported External Crystal / External Clocks The only frequency supported by SAM-BA Monitor to allow USB communication is a 12 MHz crystal or external clock. 11.5.3.
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The device also handles some class requests defined in the CDC class. Table 11-6. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 11.5.3.
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12. Boot Sequence Controller (BSC) 12.1 Description The System Controller embeds a Boot Sequence Configuration Register to save timeout delays on boot. The boot sequence is programmable through the Boot Sequence Configuration Register (BSC_CR). This register is powered by VDDBU, the modification is saved and applied after the next reset. The register is taking Factory Value in case of battery removing. This register is programmable with user programs or SAM-BA and it is key-protected. 12.
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12.4 Boot Sequence Controller (BSC) User Interface Table 12-1. Register Mapping Offset 0x0 Register Name Boot Sequence Configuration Register BSC_CR Access Reset Read-write – 12.4.
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13. Advanced Interrupt Controller (AIC) 13.1 Description The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
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13.3 Block Diagram Figure 13-1. Block Diagram FIQ AIC ARM Processor IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded nFIQ nIRQ Peripheral Embedded Peripheral APB 13.4 Application Block Diagram Figure 13-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 13.
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13.6 I/O Line Description Table 13-1. I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0 - IRQn Interrupt 0 - Interrupt n Input 13.7 Product Dependencies 13.7.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function.
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13.8 Functional Description 13.8.1 Interrupt Source Control 13.8.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode.
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Figure 13-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Edge Fast Interrupt Controller or Priority Controller AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR Figure 13-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg.
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13.8.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: z The time the software masks the interrupts. z Occurrence, either at the processor level or at the AIC level. z The execution time of the instruction in progress when the interrupt occurs. z The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations.
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Figure 13-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active Figure 13-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 13.8.3 Normal Interrupt 13.8.3.
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When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is reasserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written.
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z Pushes the current level and the current interrupt number on to the stack. z Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt.
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13.8.4.4 Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2.
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The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR). The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR).
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3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification.
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13.9 Write Protection Registers To prevent any single software error that may corrupt AIC behavior, the registers listed below can be write-protected by setting the WPEN bit in the AIC Write Protect Mode Register (AIC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the AIC Write Protect Status Register (AIC_WPSR) is set and the WPVSRC field indicates in which register the write access has been attempted.
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13.10 Advanced Interrupt Controller (AIC) User Interface 13.10.1 Base Address The AIC is mapped at the address 0xFFFFF000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset. Table 13-3.
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13.10.2 AIC Source Mode Register Name: AIC_SMR0..
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13.10.3 AIC Source Vector Register Name: AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.
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13.10.4 AIC Interrupt Vector Register Name: AIC_IVR Address: 0xFFFFF100 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV • IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt.
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13.10.5 AIC FIQ Vector Register Name: AIC_FVR Address: 0xFFFFF104 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
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13.10.6 AIC Interrupt Status Register Name: AIC_ISR Address: 0xFFFFF108 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – IRQID • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number.
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13.10.
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13.10.
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13.10.9 AIC Core Interrupt Status Register Name: AIC_CISR Address: 0xFFFFF114 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ • NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active.
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13.10.10 AIC Interrupt Enable Command Register Name: AIC_IECR Address: 0xFFFFF120 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Enable 0 = No effect.
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13.10.11 AIC Interrupt Disable Command Register Name: AIC_IDCR Address: 0xFFFFF124 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect.
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13.10.12 AIC Interrupt Clear Command Register Name: AIC_ICCR Address: 0xFFFFF128 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Clear 0 = No effect.
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13.10.13 AIC Interrupt Set Command Register Name: AIC_ISCR Address: 0xFFFFF12C Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect.
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13.10.14 AIC End of Interrupt Command Register Name: AIC_EOICR Address: 0xFFFFF130 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – – The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
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13.10.15 AIC Spurious Interrupt Vector Register Name: AIC_SPU Address: 0xFFFFF134 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register.
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13.10.16 AIC Debug Control Register Name: AIC_DCR Address: 0xFFFFF138 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – GMSK PROT This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register • PROT: Protection Mode 0 = The Protection Mode is disabled.
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13.10.17 AIC Fast Forcing Enable Register Name: AIC_FFER Address: 0xFFFFF140 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Enable 0 = No effect.
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13.10.18 AIC Fast Forcing Disable Register Name: AIC_FFDR Address: 0xFFFFF144 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Disable 0 = No effect.
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13.10.20 AIC Write Protect Mode Register Name: AIC_WPMR Address: 0xFFFFF1E4 Access: Read-write Reset: See Table 13-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII).
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13.10.21 AIC Write Protect Status Register Name: AIC_WPSR Address: 0xFFFFF1E8 Access: Read-only Reset: See Table 13-3 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the AIC_WPSR register.
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14. Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.
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14.3 Block Diagram Figure 14-1.
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14.4 Functional Description 14.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: z proc_nreset: Processor reset line. It also resets the Watchdog Timer. z backup_nreset: Affects all the peripherals powered by VDDBU. z periph_nreset: Affects the whole set of embedded peripherals. z nrst_out: Drives the NRST pin.
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named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset.
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Figure 14-4. General Reset State SLCK Any Freq. MCK Backup Supply POR output Startup Time Main Supply POR output backup_nreset Processor Startup proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles BMS Sampling 14.4.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset.
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Figure 14-5. Wake-up Reset SLCK Any Freq. MCK Main Supply POR output backup_nreset Resynch. 2 cycles Processor Startup proc_nreset RSTTYP XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 14.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin When a falling edge occurs on NRST (reset activation), internal reset lines are immediately asserted. The Processor Reset and the Peripheral Reset are asserted.
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Figure 14-6. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Processor Startup proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 14.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: z PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
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Figure 14-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 to 2 cycles Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 14.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.
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Figure 14-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 14.4.
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14.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: z RSTTYP field: This field gives the type of the last reset, as explained in previous sections. z SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
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14.5 Reset Controller (RSTC) User Interface Table 14-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 Note: Access Reset Back-up Reset RSTC_CR Write-only - Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 Mode Register RSTC_MR Read-write - 0x0000_0000 The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
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14.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFE00 Access Type: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect.
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14.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFE04 Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
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14.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFE08 Access Type: Read-write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 – KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 – 3 – ERSTL 2 – • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds.
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15. Real-time Clock (RTC) 15.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.
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15.3 Block Diagram Figure 15-1.
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15.4 Product Dependencies 15.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 15.4.2 Interrupt Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts. Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first.
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15.5.4 Error Checking when Programming Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag.
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Figure 15-2.
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15.6 Real-time Clock (RTC) User Interface Table 15-1.
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15.6.1 RTC Control Register Name: RTC_CR Address: 0xFFFFFEB0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters.
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15.6.2 RTC Mode Register Name: RTC_MR Address: 0xFFFFFEB4 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected.
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15.6.3 RTC Time Register Name: RTC_TIMR Address: 0xFFFFFEB8 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units.
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15.6.4 RTC Calendar Register Name: RTC_CALR Address: 0xFFFFFEBC Access: Read-write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units.
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15.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0xFFFFFEC0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled.
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15.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0xFFFFFEC4 Access: Read-write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled.
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15.6.7 RTC Status Register Name: RTC_SR Address: 0xFFFFFEC8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 (FREERUN) = Time and calendar registers cannot be updated. 1 (UPDATE) = Time and calendar registers can be updated.
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15.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0xFFFFFECC Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0 = No effect.
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15.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0xFFFFFED0 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect.
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15.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0xFFFFFED4 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect.
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15.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0xFFFFFED8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled.
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15.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0xFFFFFEDC Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed.
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16. Periodic Interval Timer (PIT) 16.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.
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16.3 Block Diagram Figure 16-1.
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16.4 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
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16.5 Periodic Interval Timer (PIT) User Interface Table 16-1.
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16.5.1 Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFE30 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 14 13 12 25 PITIEN 24 PITEN 17 16 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
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16.5.2 Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFE34 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
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16.5.3 Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFE38 Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.
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16.5.4 Periodic Interval Timer Image Register Name: PIT_PIIR Address: 0xFFFFFE3C Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
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17. Watchdog Timer (WDT) 17.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 17.
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17.3 Block Diagram Figure 17-1.
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17.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
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Figure 17-2.
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17.5 Watchdog Timer (WDT) User Interface Table 17-1.
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17.5.1 Watchdog Timer Control Register Register Name: WDT_CR Address: 0xFFFFFE40 Access Type: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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17.5.2 Watchdog Timer Mode Register Register Name: WDT_MR Address: 0xFFFFFE44 Access Type: Read-write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 18 11 10 22 26 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
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17.5.3 Watchdog Timer Status Register Register Name: WDT_SR Address: 0xFFFFFE48 Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
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18. Shutdown Controller (SHDWC) 18.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 18.2 Embedded Characteristics z 18.3 Shutdown and Wake-up Logic z Software Assertion of the SHDW Output Pin z Programmable De-assertion from the WKUP Input Pins Block Diagram Figure 18-1.
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18.4 I/O Lines Description Table 18-1. I/O Lines Description Name Description Type WKUP0 Wake-up 0 input Input SHDN Shutdown output Output 18.5 Product Dependencies 18.5.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller. 18.6 Functional Description The Shutdown Controller manages the main power supply.
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18.7 Shutdown Controller (SHDWC) User Interface Table 18-2.
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18.7.1 Shutdown Control Register Name: SHDW_CR Address: 0xFFFFFE10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SHDW • SHDW: Shutdown Command 0 = No effect. 1 = If KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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18.7.2 Shutdown Mode Register Name: SHDW_MR Address: 0xFFFFFE14 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWKEN 16 – 15 14 13 12 11 – 10 – 9 3 – 2 – 1 – 7 6 5 4 CPTWK0 8 – 0 WKMODE0 • WKMODE0: Wake-up Mode 0 WKMODE[1:0] Wake-up Input Transition Selection 0 0 None.
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18.7.3 Shutdown Status Register Name: SHDW_SR Address: 0xFFFFFE18 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWK 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WAKEUP0 • WAKEUP0: Wake-up 0 Status 0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
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19. General Purpose Backup Registers (GPBR) 19.1 Description The System Controller embeds Four General-purpose Backup Registers. 19.
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19.3 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset 0x0 ... 0xc Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 3 SYS_GPBR3 Access Reset Read-write – ... ... Read-write – 19.3.
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20. Slow Clock Controller (SCKC) 20.1 Description The System Controller embeds a Slow Clock Controller. The slow clock can be generated either by an external 32768 Hz crystal oscillator or by the on-chip 32 kHz RC oscillator. The 32768 Hz crystal oscillator can be bypassed by setting the OSC32BYP bit to accept an external slow clock on XIN32.
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20.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator To switch from the internal 32 kHz RC oscillator to the 32768 Hz crystal oscillator, the programmer must execute the following sequence: z Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller. z Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1. z Wait 32768 Hz Startup Time for clock stabilization (software loop).
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20.4 Slow Clock Configuration (SCKC) User Interface Table 20-1.
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20.4.1 Slow Clock Configuration Register Name: SCKC_CR Address: 0xFFFFFE50 Access: Read-write Reset: 0x0000_0001 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCSEL 2 OSC32BYP 1 OSC32EN 0 RCEN • RCEN: Internal 32 kHz RC Oscillator 0: 32 kHz RC oscillator is disabled. 1: 32 kHz RC oscillator is enabled. • OSC32EN: 32768 Hz Oscillator 0: 32768 Hz oscillator is disabled.
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21. Clock Generator (CKGR) 21.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 22.13 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 21.
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21.3 CKGR Block Diagram Figure 21-1.
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21.4 Slow Clock Selection The slow clock can be generated either by an external 32768 Hz crystal or by the on-chip 32 kHz RC oscillator. The 32768 Hz crystal oscillator can be bypassed by setting the bit OSC32BYP to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1, respectively, RCEN bit and OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source. Figure 21-2.
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21.4.3 Switch from the 32768 Hz Crystal to Internal 32 kHz RC Oscillator The same procedure must be followed to switch from a 32768 Hz crystal to the internal 32 kHz RC oscillator. z Switch the master clock to a source different from slow clock (PLL or Main Oscillator). z Enable the internal 32 kHz RC oscillator for low power by setting the bit RCEN to 1 z Wait internal 32 kHz RC Startup Time for clock stabilization (software loop).
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21.4.
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21.5 Main Clock Figure 21-3.
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21.6 Main Clock Selection The main clock can be generated either by an external 12 MHz crystal oscillator or by the on-chip 12 MHz RC oscillator. This fast RC oscillator allows the processor to start or restart in a few microseconds when 12 MHz internal RC is selected. The 12 MHz crystal oscillator can be bypassed by setting the bit MOSCXTBY to accept an external main clock on XIN. Figure 21-4.
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21.6.2 Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal For USB operations an external 12 MHz crystal is required for better accuracy. The programmer controls the main clock switching by software and so must take precautions during the switching phase. To switch from internal 12 MHz RC oscillator to the 12 MHz crystal, the programmer must execute the following sequence: z Enable the 12 MHz oscillator by setting the bit MOSCXTEN to 1.
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counting down on the slow clock divided by 8 from the MOSCXTCNT value. Since the MOSCXTCNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor. 21.6.7 Main Clock Oscillator Selection The user can select either the 12 MHz Fast RC Oscillator or the 12 to 16 MHz Crystal Oscillator to be the source of Main Clock.
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21.7.1 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. The PLLA allows multiplication of the divider’s outputs.
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22. Power Management Controller (PMC) 22.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core. 22.2 Embedded Characteristics The Power Management Controller provides all the clock signals to the system.
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22.3 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler.
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22.4 Block Diagram Figure 22-2. General Clock Block Diagram PLLACK USBS UHP48M USBDIV+1 /4 UHP12M USB OHCI USB EHCI Prescaler /1,/2,/3,/4,...,/64 DDRCK X /1 /1.5 /2 2x MCK /1 /2 MCK /3 /4 Master Clock Controller SLCK MAINCK int /2 Divider MAINCK SLCK PCK Processor Clock Controller UPLLCK Peripherals Clock Controller ON/OFF Divider Periph_clk[..] ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] UPLLCK Programmable Clock Controller 22.
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22.6 USB Device and Host Clocks The USB Device and Host High Speed ports clocks are controlled by the UDPHS and UHPHS bits in PMC_PCER. To save power on this peripheral when they are is not used, the user can set these bits in PMC_PCDR. The UDPHS and UHPHS bits in PMC_PCR give the activity of these clocks. The PMC also provides the clocks UHP48M and UHP12M to the USB Host OHCI. The USB Host OHCI clocks are controlled by the UHP bit in PMC_SCER.
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22.10 Programmable Clock Output Controller The PMC controls 2 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock, the Master Clock, the PLLACK/PLLADIV2, the UTMI PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
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3. Setting Bias and High Speed PLL (UPLL) for UTMI The UTMI PLL is enabled by setting the UPLLEN field in the CKGR_UCKR register. The UTMI Bias must is enabled by setting the BIASEN field in the CKGR_UCKR register in the same time. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the PLLCOUNT field in the CKGR_UCKR register. Once this register has been correctly configured, the user must wait for LOCKU field in the PMC_SR register to be set.
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Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1) The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 5. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 2 programmable clocks can be enabled or disabled.
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22.12 Clock Switching Details 22.12.1 Master Clock Switching Timings Table 22-1 and Table 22-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 22-1. Clock Switching Timings (Worst Case) Fro m Main Clock SLCK PLL Clock Main Clock – 4 x SLCK + 2.5 x Main Clock SLCK 0.
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22.12.2 Clock Switching Waveforms Figure 22-3. Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 22-4.
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Figure 22-5. Change PLLA Programming Slow Clock PLLA Clock LOCKA MCKRDY Master Clock Slow Clock Write CKGR_PLLAR Figure 22-6.
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22.13 Power Management Controller (PMC) User Interface Table 22-3. Register Mapping Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only N.A. 0x0004 System Clock Disable Register PMC_SCDR Write-only N.A. 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0005 0x0010 Peripheral Clock Enable Register PMC _PCER Write-only N.A.
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22.13.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0xFFFFFC00 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – SMDCK – DDRCK – – • DDRCK: DDR Clock Enable 0 = No effect. 1 = Enables the DDR clock. • SMDCK: SMD Clock Enable 0 = No effect. 1 = Enables the soft modem clock.
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22.13.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0xFFFFFC04 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – SMDCK – DDRCK – PCK • PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode. • DDRCK: DDR Clock Disable 0 = No effect.
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22.13.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0xFFFFFC08 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – SMDCK – DDRCK – PCK • PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled. • DDRCK: DDR Clock Status 0 = The DDR clock is disabled.
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22.13.4 PMC Peripheral Clock Enable Register Name: PMC_PCER Address: 0xFFFFFC10 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0 = No effect.
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22.13.5 PMC Peripheral Clock Disable Register Name: PMC_PCDR Address: 0xFFFFFC14 Access: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Disable 0 = No effect.
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22.13.
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22.13.7 PMC UTMI Clock Configuration Register Name: CKGR_UCKR Address: 0xFFFFFC1C Access: Read-write 31 30 29 28 27 – 26 – 25 – 24 BIASEN 21 20 19 – 18 – 17 – 16 UPLLEN BIASCOUNT 23 22 UPLLCOUNT 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • UPLLEN: UTMI PLL Enable 0 = The UTMI PLL is disabled. 1 = The UTMI PLL is enabled. When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
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22.13.8 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0xFFFFFC20 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 CFDEN 24 MOSCSEL 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 – 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 – 5 – 4 – • KEY: Password Should be written at value 0x37. Writing any other value in this field aborts the write operation.
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22.13.9 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0xFFFFFC24 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINFRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled.
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22.13.10 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read-write 31 – 30 – 29 1 28 – 23 22 21 20 27 – 26 25 MULA 24 19 18 17 16 10 9 8 2 1 0 MULA 15 14 13 12 11 OUTA 7 PLLACOUNT 6 5 4 3 DIVA Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
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22.13.
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22.13.12 PMC USB Clock Register Name: PMC_USB Address: 0xFFFFFC38 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – USBDIV 7 6 5 4 3 2 1 0 – – – – – – – USBS • USBS: USB OHCI Input Clock Selection 0 = USB Clock Input is PLLA 1 = USB Clock Input is UPLL • USBDIV: Divider for USB OHCI Clock.
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22.13.13 PMC SMD Clock Register Name: PMC_SMD Address: 0xFFFFFC3C Access : Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – SMDDIV 7 6 5 4 3 2 1 0 – – – – – – – SMDS • SMDS: SMD input clock selection 0 = SMD Clock Input is PLLA 1 = SMD Clock Input is UPLL • SMDDIV: Divider for SMD Clock.
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22.13.
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22.13.
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22.13.
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22.13.17 PMC Status Register Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – FOS CFDS CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 – – – – – – PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 OSCSELS LOCKU – – MCKRDY – LOCKA MOSCXTS • MOSCXTS: Main XTAL Oscillator Status 0 = Main XTAL oscillator is not stabilized. 1 = Main XTAL oscillator is stabilized.
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• CFDEV: Clock Failure Detector Event 0 = No clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. 1 = At least one clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. • CFDS: Clock Failure Detector Status 0 = A clock failure of the main on-chip RC oscillator clock is not detected. 1 = A clock failure of the main on-chip RC oscillator clock is detected.
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22.13.
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22.13.
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22.13.20 PMC Write Protect Mode Register Name: PMC_WPMR Address: 0xFFFFFCE4 Access: Read-write Reset: See Table 22-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
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22.13.21 PMC Write Protect Status Register Name: PMC_WPSR Address: 0xFFFFFCE8 Access: Read-only Reset: See Table 22-3 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register.
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22.13.22 PMC Peripheral Control Register Name: PMC_PCR Address: 0xFFFFFD0C Access: Read-write 31 — 30 — 29 — 28 EN 27 — 26 — 25 — 24 — 23 — 22 — 21 — 20 — 19 — 18 — 17 15 — 14 — 13 — 12 CMD 11 — 10 — 9 — 8 — 7 — 6 — 5 4 3 2 1 0 16 DIV PID • PID: Peripheral ID Only the following Peripheral IDs can have a DIV value other than 0: PID2, PID3, PID5 to PID11, PID13 to PID19, PID28 to PID30.
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23. Parallel Input/Output (PIO) Controller 23.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
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23.3 Block Diagram Figure 23-1. Block Diagram PIO Controller Interrupt Controller PIO Interrupt PIO Clock PMC Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 23-2.
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23.4 Product Dependencies 23.4.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
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23.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 23-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 23-3.
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23.5.1 Pull-up and Pull-down Resistor Control Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
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23.5.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers) determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven.
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Figure 23-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 23.5.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.
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The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals.
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These Additional Modes are: z Rising Edge Detection z Falling Edge Detection z Low Level Detection z High Level Detection In order to select an Additional Interrupt Mode: z The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR (Edge Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level Detection. The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status Register).
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z Rising edge on PIO line 7 z Any edge on the other lines The configuration required is described below. 23.5.10.2Interrupt Mode Configuration All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. 23.5.10.3Edge or Level Detection Configuration Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR.
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Only PADs PA[20:15], PA[13:11] and PA[4:2] can be configured. When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. When programming 0xF in fields, the propagation delay of the corresponding pad is maximal. Figure 23-9. Programmable I/O Delays PAin[0] PIO PAout[0] Programmable Delay Line DELAY1 PAin[1] PAout[1] Programmable Delay Line DELAY2 PAin[2] PAout[2] Programmable Delay Line DELAYx 23.5.
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z “PIO Pull Up Enable Register” on page 241 z “PIO Peripheral ABCD Select Register 1” on page 243 z “PIO Peripheral ABCD Select Register 2” on page 244 z “PIO Output Write Enable Register” on page 249 z “PIO Output Write Disable Register” on page 249 z “PIO Pad Pull Down Disable Register” on page 247 z “PIO Pad Pull Down Status Register” on page 248 SAM9G25 [DATASHEET] 11032C–ATARM–25-Jan-13 226
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23.6 I/O Lines Programming Example The programing example as shown in Table 23-1 below is used to obtain the following configuration.
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23.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is notmultiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 23-2.
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Table 23-2.
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Table 23-2. Register Mapping (Continued) Offset Register Name 0x0118 I/O Drive Register 2 PIO_DRIVER2 0x011C Reserved 0x0120 to 0x014C Reserved Access Reset Read-write 0x00000000 Notes: 1. Reset value depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines.
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23.7.
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23.7.3 PIO Status Register Name: PIO_PSR Address: 0xFFFFF408 (PIOA), 0xFFFFF608 (PIOB), 0xFFFFF808 (PIOC), 0xFFFFFA08 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active).
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23.7.
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23.7.
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23.7.
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23.7.11 PIO Clear Output Data Register Name: PIO_CODR Address: 0xFFFFF434 (PIOA), 0xFFFFF634 (PIOB), 0xFFFFF834 (PIOC), 0xFFFFFA34 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Clear Output Data 0: No effect.
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23.7.13 PIO Pin Data Status Register Name: PIO_PDSR Address: 0xFFFFF43C (PIOA), 0xFFFFF63C (PIOB), 0xFFFFF83C (PIOC), 0xFFFFFA3C (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The I/O line is at level 0.
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23.7.15 PIO Interrupt Disable Register Name: PIO_IDR Address: 0xFFFFF444 (PIOA), 0xFFFFF644 (PIOB), 0xFFFFF844 (PIOC), 0xFFFFFA44 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0: No effect.
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23.7.
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23.7.
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23.7.
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23.7.23 PIO Pull Up Status Register Name: PIO_PUSR Address: 0xFFFFF468 (PIOA), 0xFFFFF668 (PIOB), 0xFFFFF868 (PIOC), 0xFFFFFA68 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0: Pull Up resistor is enabled on the I/O line.
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23.7.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read-write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” . • P0-P31: Peripheral Select.
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23.7.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Access: Read-write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” . • P0-P31: Peripheral Select.
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23.7.26 PIO Input Filter Slow Clock Disable Register Name: PIO_IFSCDR Address: 0xFFFFF480 (PIOA), 0xFFFFF680 (PIOB), 0xFFFFF880 (PIOC), 0xFFFFFA80 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Clock Glitch Filtering Select. 0: No Effect.
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23.7.35 PIO Output Write Status Register Name: PIO_OWSR Address: 0xFFFFF4A8 (PIOA), 0xFFFFF6A8 (PIOB), 0xFFFFF8A8 (PIOC), 0xFFFFFAA8 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0: Writing PIO_ODSR does not affect the I/O line.
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23.7.37 PIO Additional Interrupt Modes Disable Register Name: PIO_AIMDR Address: 0xFFFFF4B4 (PIOA), 0xFFFFF6B4 (PIOB), 0xFFFFF8B4 (PIOC), 0xFFFFFAB4 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Additional Interrupt Modes Disable. 0: No effect.
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23.7.39 PIO Edge Select Register Name: PIO_ESR Address: 0xFFFFF4C0 (PIOA), 0xFFFFF6C0 (PIOB), 0xFFFFF8C0 (PIOC), 0xFFFFFAC0 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge Interrupt Selection. 0: No effect.
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23.7.41 PIO Edge/Level Status Register Name: PIO_ELSR Address: 0xFFFFF4C8 (PIOA), 0xFFFFF6C8 (PIOB), 0xFFFFF8C8 (PIOC), 0xFFFFFAC8 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge/Level Interrupt source selection.
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23.7.43 PIO Rising Edge/High Level Select Register Name: PIO_REHLSR Address: 0xFFFFF4D4 (PIOA), 0xFFFFF6D4 (PIOB), 0xFFFFF8D4 (PIOC), 0xFFFFFAD4 (PIOD) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Rising Edge /High Level Interrupt Selection.
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23.7.45 PIO Lock Status Register Name: PIO_LOCKSR Address: 0xFFFFF4E0 (PIOA), 0xFFFFF6E0 (PIOB), 0xFFFFF8E0 (PIOC), 0xFFFFFAE0 (PIOD) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Lock Status. 0: The I/O line is not locked. 1: The I/O line is locked.
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23.7.46 PIO Write Protect Mode Register Name: PIO_WPMR Address: 0xFFFFF4E4 (PIOA), 0xFFFFF6E4 (PIOB), 0xFFFFF8E4 (PIOC), 0xFFFFFAE4 (PIOD) Access: Read-write Reset: See Table 23-2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – – – For more information on Write Protection Registers, refer to Section 23.7 ”Parallel Input/Output Controller (PIO) User Interface”.
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23.7.47 PIO Write Protect Status Register Name: PIO_WPSR Address: 0xFFFFF4E8 (PIOA), 0xFFFFF6E8 (PIOB), 0xFFFFF8E8 (PIOC), 0xFFFFFAE8 (PIOD) Access: Read-only Reset: See Table 23-2 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 – WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – – – • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the PIO_WPSR register.
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23.7.50 PIO I/O Drive Register 1 Name: PIO_DRIVER1 Address: 0xFFFFF514 (PIOA), 0xFFFFF714 (PIOB), 0xFFFFF914 (PIOC), 0xFFFFFB14 (PIOD) Access: Read-write Reset: 0x0 31 30 29 LINE15 23 22 21 LINE11 15 28 14 20 13 19 6 12 5 18 11 17 9 8 LINE4 2 LINE1 16 LINE8 10 3 24 LINE12 LINE5 4 LINE2 25 LINE9 LINE6 LINE3 26 LINE13 LINE10 LINE7 7 27 LINE14 1 0 LINE0 • LINEx [x=0..
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23.7.51 PIO I/O Drive Register 2 Name: PIO_DRIVER2 Address: 0xFFFFF518 (PIOA), 0xFFFFF718 (PIOB), 0xFFFFF918 (PIOC), 0xFFFFFB18 (PIOD) Access: Read-write Reset: 0x0 31 30 29 LINE31 23 22 21 LINE27 15 27 14 20 13 19 6 12 5 18 11 17 9 8 LINE20 2 LINE17 16 LINE24 10 3 24 LINE28 LINE21 4 LINE18 25 LINE25 LINE22 LINE19 26 LINE29 LINE26 LINE23 7 28 LINE30 1 0 LINE16 • LINEx [x=16..
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24. Debug Unit (DBGU) 24.1 Description The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARMbased systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication.
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24.3 Block Diagram Figure 24-1. Debug Unit Functional Block Diagram Peripheral Bridge DMA Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive DRXD COMMRX ARM Processor COMMTX DCC Handler Chip ID nTRST ICE Access Handler Interrupt Control dbgu_irq Power-on Reset force_ntrst Table 24-1. Debug Unit Pin Description Pin Name Description Type DRXD Debug Receive Data Input DTXD Debug Transmit Data Output Figure 24-2.
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24.4 Product Dependencies 24.4.1 I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. Table 24-2. I/O Lines Instance Signal I/O Line Peripheral DBGU DRXD PA9 A DBGU DTXD PA10 A 24.4.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller.
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Figure 24-3. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 24.5.2 Receiver 24.5.2.1 Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
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Figure 24-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 24.5.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 24-6.
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24.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 24-9.
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Figure 24-11.Transmitter Control DBGU_THR Data 0 Data 1 Shift Register DTXD Data 0 S Data 0 Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 24.5.4 DMA Support Both the receiver and the transmitter of the Debug Unit’s UART are connected to a DMA Controller (DMAC) channel. The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface. 24.5.5 Test Modes The Debug Unit supports three tests modes.
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Figure 24-12.Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter TXD VDD Disabled Disabled RXD TXD 24.5.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
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24.5.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
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24.6 Debug Unit (DBGU) User Interface Table 24-3.
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24.6.1 Debug Unit Control Register Name: DBGU_CR Address: 0xFFFFF200 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
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24.6.6 Debug Unit Status Register Name: DBGU_SR Address: 0xFFFFF214 Access: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
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24.6.7 Debug Unit Receiver Holding Register Name: DBGU_RHR Address: 0xFFFFF218 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set. 24.6.
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24.6.
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24.6.10 Debug Unit Chip ID Register Name: DBGU_CIDR Address: 0xFFFFF240 Access: Read-only 31 30 29 EXT 23 28 27 26 NVPTYP 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 EPROC 3 2 VERSION • VERSION: Version of the Device Values depend upon the version of the device.
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Value Name Description 13 – Reserved 14 2048K 2048K bytes 15 – Reserved • NVPSIZ2 Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8K bytes 2 16K 16K bytes 3 32K 32K bytes 4 – Reserved 5 64K 64K bytes 6 Reserved 7 128K 128K bytes 8 – Reserved 9 256K 256K bytes 10 512K 512K bytes 11 – Reserved 12 1024K 1024K bytes 13 – Reserved 14 2048K 2048K bytes 15 – Reserved • SRAMSIZ: Internal SRAM Size Value Name Description
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Value Name Description 13 256K 256K bytes 14 96K 96K bytes 15 512K 512K bytes • ARCH: Architecture Identifier Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x40 AT91x40 AT91x40 Series 0x42 AT91x42 AT91x42 Series 0x55 AT91x55 AT91x55 Series 0x60 AT91SAM7Axx AT91SAM7Axx Series 0x61 AT91SAM7AQxx AT91SAM7AQxx Series 0x63
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Value Name Description 0x9A ATSAM3SDxC ATSAM3SDxC Series (100-pin version) 0xA5 – Reserved 0xF0 AT75Cxx AT75Cxx Series • NVPTYP: Nonvolatile Program Memory Type Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on-chip Flash 4 SRAM SRAM emulating ROM 2 FLASH Embedded Flash Memory 3 ROM_FLASH ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size • EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exist
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24.6.11 Debug Unit Chip ID Extension Register Name: DBGU_EXID Address: 0xFFFFF244 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
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24.6.12 Debug Unit Force NTRST Register Name: DBGU_FNR Address: 0xFFFFF248 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST • FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor’s TAP controller is held low.
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25. Bus Matrix (MATRIX) 25.1 Description The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
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25.2.1 Matrix Masters The Bus Matrix manages 12 masters, which means that each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 25-1.
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25.2.3 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. Table 25-3. Master to Slave Access Masters 0 1 2&3 Slaves ARM926 Instr.
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default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to Section 25.7.2 “Bus Matrix Slave Configuration Registers”. 25.4.1 No Default Master After the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency clock cycle for the first access of a burst after bus Idle.
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1. Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. Single Cycles: When a slave is currently doing a single access. 3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. See Section 25.5.1.1 “Undefined Length Burst Arbitration” 4.
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25.5.2 Arbitration Priority Scheme The bus Matrix arbitration scheme is organized in priority pools. Round-robin priority is used in the highest and lowest priority pools, whereas fixed level priority is used between priority pools and in the intermediate priority pools. For each slave, each master is assigned to one of the slave priority pools through the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS).
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25.7 Bus Matrix (MATRIX) User Interface Table 25-4.
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Table 25-4.
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25.7.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0...
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25.7.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...
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25.7.3 Bus Matrix Priority Registers A For Slaves Name: MATRIX_PRAS0...
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25.7.4 Bus Matrix Priority Registers B For Slaves Name: MATRIX_PRBS0...
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25.7.6 Chip Configuration User Interface Table 25-5.
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25.7.6.1 EBI Chip Select Assignment Register Name: CCFG_EBICSA Access: Read-write Reset: 0x0000_0000 31 30 29 28 27 26 25 24 – – – – – – DDR_MP_EN NFD0_ON_D16 23 22 21 20 19 18 17 16 – – – – – – EBI_DRIVE – 15 14 13 12 11 10 9 8 – – – – – – EBI_DBPDC EBI_DBPUC 7 6 5 4 3 2 1 0 – – – – EBI_CS3A – EBI_CS1A – • EBI_CS1A: EBI Chip Select 1 Assignment 0 = EBI Chip Select 1 is assigned to the Static Memory Controller.
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Table 25-6. Connection examples with various VDDNF and VDDIOM NFD0_ON_D16 Signals VDDIOM VDDNF External Memory 0 NFD0 = D0, ..., NFD15 = D15 1.8V 1.8V DDR2 or LPDDR or LPSDR + NAND Flash 1.8V 0 NFD0 = D0, ..., NFD15 = D15 3.3V 3.3V 32-bit SDR + NAND Flash 3.3V 1 NFD0 = D16, ..., NFD15 = D31 1.8V 1.8V DDR2 or LPDDR or LPSDR + NAND Flash 1.8V 1 NFD0 = D16, ..., NFD15 = D31 1.8V 3.3V DDR2 or LPDDR or LPSDR + NAND Flash 3.3V 1 NFD0 = D16, ..., NFD15 = D31 3.3V 1.
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25.7.7 Write Protect Mode Register Name: MATRIX_WPMR Address: 0xFFFFDFE4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN For more details on MATRIX_WPMR, refer to Section 25.6 “Write Protect Registers” on page 290. • WPEN: Write Protect ENable 0 = Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
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25.7.8 Write Protect Status Register Name: MATRIX_WPSR Address: 0xFFFFDFE8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS For more details on MATRIX_WPSR, refer to Section 25.6 “Write Protect Registers” on page 290. • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR.
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26. External Bus Interface (EBI) 26.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, DDR, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, DDR2 and SDRAM.
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26.
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26.3 EBI Block Diagram Figure 26-1.
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26.4 I/O Lines Description Table 26-1.
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26.5 Application Example 26.5.1 Hardware Interface Table 26-3 on page 307 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 26-3.
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Table 26-4.
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Table 26-4. EBI Pins and External Device Connections Signals: EBI_ Power supply Pins of the Interfaced Device DDR2/LPDDR SDR/LPSDR NAND Flash DDRC SDRAMC NFC Controller CAS VDDIOM CAS CAS – SDWE VDDIOM WE WE – Pxx VDDNF – – CE VDDNF – – RDY Pxx Note: 1. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D7 or D16-D24 depending on memory power supplies. This switch is located in the EBICSA register in the Bus Matrix user interface. 26.5.
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At reset the selected current drive is LOW. To improve EMI, programmable delay has been inserted on lines able to run at high speed. The control of these delays is as follows: z EBI (DDR2SDRC\SMC\NAND Flash) D[15:0] controlled by 2 registers DELAY1 and DELAY2 located in the SMC user interface. z D[0] <=> DELAY1[3:0], z D[1] <=> DELAY1[7:4],..., z D[6] <=> DELAY1[27:24], z D[7] <=> DELAY1[31:28] z D[8] <=> DELAY2[3:0], z D[9] <=> DELAY2[7:4],...
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26.5.3.4 Power supplies The product embeds a dual power supply for EBI. VDDNF for NAND Flash signals and VDDIOM for others. This allows to use an 1.8V or 3.3V NAND Flash independently of SDRAM power supply. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D15 or D16-D32 depending on memory power supplies. This switch is located in the register EBICSA in the Bus Matrix user interface.
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26.5.3.5 Static Memory Controller For information on the Static Memory Controller, refer to the Static Memory Controller section of this datazsheet. 26.5.3.6 DDR2SDRAM Controller The product embeds a multi-port DDR2SDR Controller. This allows to use three additional ports on DDR2SDRC to lessen the EBI load from a part of DDR2 or LP-DDR accesses. This increases the bandwidth when DDR2 and NAND Flash devices are used. This feature is NOT compatible with SDR or LP-SDR Memory.
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NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines.
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26.5.4 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 26.5.4.1 2x8-bit DDR2 on EBI Hardware Configuration Software Configuration z Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Register located in the bus matrix memory space. z Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency.
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26.5.4.2 16-bit LPDDR on EBI Hardware Configuration Software Configuration The following configuration has to be performed: z Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip Select Register located in the bus matrix memory space. z Initialize the DDR2 Controller depending on the LP-DDR device and system bus frequency. The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initialization” in “DDR/SDR SDRAM Controller (DDRSDRC)”.
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26.5.4.3 16-bit SDRAM on EBI Hardware Configuration Software Configuration The following configuration has to be performed: z Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. z Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits.
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26.5.4.4 2x16-bit SDRAM on EBI Hardware Configuration A[1..14] D[0..31] SDRAM MN1 VDDIOM A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 23 24 25 26 29 30 31 32 33 34 22 35 BA0 BA1 20 21 A14 36 40 CKE 37 CLK 38 DQM0 DQM1 15 39 CAS RAS 17 18 WE 16 19 R1 470K MN2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.
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26.5.4.5 8-bit NAND Flash with NFD0_ON_D16 = 0 Hardware Configuration D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
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26.5.4.6 16-bit NAND Flash with NFD0_ON_D16 = 0 Hardware Configuration D[0..15] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C 10K MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.
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26.5.4.7 8-bit NAND Flash with NFD0_ON_D16 = 1 Hardware Configuration Software Configuration The following configuration has to be performed: z Set NFD0_ON_D16 = 1 in the EBI Chip Select Assignment Register located in the bus matrix memory space z Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register z Reserve A21 / A22 for ALE / CLE functions.
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26.5.4.8 16-bit NAND Flash with NFD0_ON_D16 = 1 Hardware Configuration Software Configuration The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller.
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26.5.4.9 NOR Flash on NCS0 Hardware Configuration D[0..15] A[1..
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27. Programmable Multibit ECC Controller (PMECC) 27.1 Description The Programmable Multibit ECC Controller (PMECC) is a programmable binary BCH (Bose, Chaudhuri and Hocquenghem) encoder/decoder. This controller can be used to generate redundancy information for both Single-Level Cell (SLC) and Multi-level Cell (MLC) NAND Flash devices. It supports redundancy for correction of 2, 4, 8, 12 or 24 bits of error per sector of data. 27.
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27.3 Block Diagram Figure 27-1.
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27.4 Functional Description The NAND Flash sector size is programmable and can be set to 512 bytes or 1024 bytes. The PMECC module generates redundancy at encoding time, when a NAND write page operation is performed. The redundancy is appended to the page and written in the spare area. This operation is performed by the processor. It moves the content of the PMECCx registers into the NAND Flash memory.
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Figure 27-2.
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27.4.1 MLC/SLC Write Page Operation using PMECC When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR field of the PMECCFG register set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error protected, then the SPAREEN bit of the PMECCFG register is set to one. When the NAND spare area contains only redundancy information, the SPAREEN bit is set to zero.
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27.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set When the SPAREEN field of the PMECC_CFG register is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When the encoding process is over, the redundancy is written to the spare area in user mode, USER field of the PMECC_CTRL must be set to one. Figure 27-3.
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27.4.2 MLC/SLC Read Page Operation using PMECC Table 27-3.
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27.4.2.2 MLC/SLC Read Operation If the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When AUTO field is set to one the ECC is retrieved automatically, otherwise the ECC must be read using user mode. Figure 27-6.
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27.5 Software Implementation 27.5.1 Remainder Substitution Procedure The substitute function evaluates the polynomial remainder, with different values of the field primitive elements. The finite field arithmetic addition operation is performed with the Exclusive or. The finite field arithmetic multiplication operation is performed through the gf_log, gf_antilog lookup tables. The REM2NP1 and REMN2NP3 fields of the PMECC_REMx registers contain only odd remainders.
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int i; int j; int k; /* mu */ int mu[NB_ERROR_MAX+2]; /* sigma ro */ int sro[2*NB_ERROR_MAX+1]; /* discrepancy */ int dmu[NB_ERROR_MAX+2]; /* delta order */ int delta[NB_ERROR_MAX+2]; /* index of largest delta */ int ro; int largest; int diff; /* */ /* First Row */ /* */ /* Mu */ mu[0] = -1; /* Actually -1/2 */ /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[0][i] = 0; smu[0][0] = 1; /* discrepancy set to 1 */ dmu[0] = 1; /* polynom order set to 0 */ lmu[0] = 0; /* delta set to -1 */ de
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/* copy previous polynom order to the next */ lmu[i+1] = lmu[i]; } else { ro = 0; largest = -1; /* find largest delta with dmu != 0 */ for (j=0; j largest) { largest = delta[j]; ro = j; } } } /* initialize signal ro */ for (k = 0; k < 2*NB_ERROR_MAX+1; k ++) { sro[k] = 0; } /* compute difference */ diff = (mu[i] - mu[ro]); /* compute X ^ (2(mu-ro)) */ for (k = 0; k < (2*NB_ERROR_MAX+1); k ++) { sro[k+diff] = smu[ro][k]; } /* multiply by dmu * dmu[ro]^-1 */ for (k = 0;
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delta[i+1] = (mu[i+1] * 2 - lmu[i+1]) >> 1; /* In either case compute the discrepancy */ for (k = 0 ; k <= (lmu[i+1]>>1); k++) { if (k == 0) dmu[i+1] = si[2*(i-1)+3]; /* check if one operand of the multiplier is null, its index is -1 */ else if (smu[i+1][k] && si[2*(i-1)+3-k]) dmu[i+1] = gf_antilog[(gf_log[smu[i+1][k]] + gf_log[si[2*(i-1)+3-k]])%nn] ^ dmu[i+1]; } } return 0; } 27.5.3 Find the Error Position The output of the get_sigma() procedure is a polynomial stored in the smu[NB_ERROR+1][] table.
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27.6 Programmable Multibit ECC Controller (PMECC) User Interface Table 27-4.
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Table 27-4.
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27.6.
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– for NAND read access: 0: The spare area is skipped. 1: The spare area contains protected data or only redundancy information. • AUTO: Automatic Mode Enable This bit is only relevant in NAND Read Mode, when spare enable is activated. 0: Indicates that the spare area is not protected. In that case the ECC computation takes into account the ECC area located in the spare area. (within the start address and the end address). 1: Indicates that the spare is error protected.
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27.6.2 PMECC Spare Area Size Register Name: PMECC_SAREA Address: 0xFFFFE004 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 SPARESIZE 0 SPARESIZE • SPARESIZE: Spare Area Size The spare area size is equal to (SPARESIZE+1) bytes.
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27.6.3 PMECC Start Address Register Name: PMECC_SADDR Address: 0xFFFFE008 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 STARTADDR 0 STARTADDR • STARTADDR: ECC Area Start Address (byte oriented address) This field indicates the first byte address of the ECC area. Location 0 matches the first byte of the spare area.
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27.6.4 PMECC End Address Register Name: PMECC_EADDR Address: 0xFFFFE00C Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 3 2 1 24 – 16 – 8 ENDADDR 0 ENDADDR • ENDADDR: ECC Area End Address (byte oriented address) This field indicates the last byte address of the ECC area.
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27.6.5 PMECC Clock Control Register Name: PMECC_CLK Address: 0xFFFFE010 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 25 – 17 – 9 – 1 CLKCTRL 24 – 16 – 8 – 0 • CLKCTRL: Clock Control Register The PMECC Module data path Setup Time is set to CLKCTRL+1. This field indicates the database setup times in number of clock cycles.
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27.6.6 PMECC Control Register Name: PMECC_CTRL Address: 0xFFFFE014 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DISABLE 28 – 20 – 12 – 4 ENABLE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 USER 25 – 17 – 9 – 1 DATA 24 – 16 – 8 – 0 RST • RST: Reset the PMECC Module When set to one, this bit reset PMECC controller, configuration registers remain unaffected.
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27.6.7 PMECC Status Register Name: PMECC_SR Address: 0xFFFFE018 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 ENABLE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 BUSY • BUSY: The Kernel of the PMECC is Busy • ENABLE: PMECC Module Status 0: The PMECC Module is disabled and can be configured. 1: The PMECC Module is enabled and the configuration registers cannot be written.
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27.6.
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27.6.
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27.6.
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27.6.11 PMECC Interrupt Status Register Name: PMECC_ISR Address: 0xFFFFE028 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 ERRIS • ERRIS: Error Interrupt Status Register When set to one, bit i of the PMECCISR register indicates that sector i is corrupted.
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27.6.12 PMECC ECC x Register Name: PMECC_ECCx [x=0..10] [sec_num=0..7] Address: 0xFFFFE040 [0][0] .. 0xFFFFE068 [10][0] 0xFFFFE080 [0][1] .. 0xFFFFE0A8 [10][1] 0xFFFFE0C0 [0][2] .. 0xFFFFE0E8 [10][2] 0xFFFFE100 [0][3] .. 0xFFFFE128 [10][3] 0xFFFFE140 [0][4] .. 0xFFFFE168 [10][4] 0xFFFFE180 [0][5] .. 0xFFFFE1A8 [10][5] 0xFFFFE1C0 [0][6] .. 0xFFFFE1E8 [10][6] 0xFFFFE200 [0][7] ..
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27.6.13 PMECC Remainder x Register Name: PMECC_REMx [x=0..11] [sec_num=0..7] Address: 0xFFFFE240 [0][0] .. 0xFFFFE26C [11][0] 0xFFFFE280 [0][1] .. 0xFFFFE2AC [11][1] 0xFFFFE2C0 [0][2] .. 0xFFFFE2EC [11][2] 0xFFFFE300 [0][3] .. 0xFFFFE32C [11][3] 0xFFFFE340 [0][4] .. 0xFFFFE36C [11][4] 0xFFFFE380 [0][5] .. 0xFFFFE3AC [11][5] 0xFFFFE3C0 [0][6] .. 0xFFFFE3EC [11][6] 0xFFFFE400 [0][7] ..
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28. Programmable Multibit ECC Error Location Controller (PMERRLOC) 28.1 Description The PMECC Error Location Controller provides hardware acceleration for determining roots of polynomials over two finite fields: GF(2^13) and GF(2^14). It integrates 24 fully programmable coefficients. These coefficients belong to GF(2^13) or GF(2^14). The coefficient programmed in the PMERRLOC_SIGMAx register is the coefficient of degree x in the polynomial. 28.2 28.
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28.4 Functional Description The PMERRLOC search operation is started as soon as a write access is detected in the ELEN register and can be disabled by writing to the ELDIS register. The ENINIT field of the ELEN register shall be initialized with the number of Galois field elements to test. The set of the roots can be limited to a valid range. Table 28-1. ENINIT field value for a sector size of 512 bytes Error Correcting Capability ENINIT Value 2 4122 4 4148 8 4200 12 4252 24 4408 Table 28-2.
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28.5 Programmable Multibit ECC Error Location Controller (PMERRLOC) User Interface Table 28-3.
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28.5.1 Error Location Configuration Register Name: PMERRLOC_ELCFG Address: 0xFFFFE600 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 27 – 19 12 – 4 – 11 – 3 – 26 – 18 ERRNUM 10 – 2 – 25 – 17 24 – 16 9 – 1 – 8 – 0 SECTORSZ • ERRNUM: Number of Errors • SECTORSZ: Sector Size 0: The ECC computation is based on a 512-byte sector. 1: The ECC computation is based on a 1024-byte sector.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.
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28.5.10 Error Location SIGMAx Register Name: PMERRLOC_SIGMAx [x=0..24] Address: 0xFFFFE628 [0] .. 0xFFFFE688 [24] Access: Read-Write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 5 4 3 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 0 SIGMAx SIGMAx • SIGMAx: Coefficient of Degree x in the SIGMA Polynomial. SIGMAx belongs to the finite field GF(2^13) when the sector size is set to 512 bytes.
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28.5.11 PMECC Error Locationx Register Name: PMERRLOC_ELx [x=0..23] Address: 0xFFFFE68C Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 5 4 3 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 0 ERRLOCN ERRLOCN • ERRLOCN: Error Position within the Set {sector area, spare area}. ERRLOCN points to 0 when the first bit of the main area is corrupted.
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29. Static Memory Controller (SMC) 29.1 Description The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
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29.3 I/O Lines Description Table 29-1.
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29.5 Application Example 29.5.1 Hardware Interface Figure 29-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 D0 - D7 128K x 8 SRAM D8-D15 D0 - D7 CS NWR0/NWE A2 - A25 A2 - A18 A0 - A16 NRD OE NWR1/NBS1 WE 128K x 8 SRAM D16 - D23 D24-D31 D0 - D7 A0 - A16 NRD Static Memory Controller 29.
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29.7 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 29-2).
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Figure 29-3. Memory Connection for an 8-bit Data Bus D[7:0] D[7:0] A[18:2] A[18:2] SMC A0 A0 A1 A1 NWE Write Enable NRD Output Enable NCS[2] Memory Enable Figure 29-4. Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC A[0] NBS0 Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Memory Enable Figure 29-5.
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29.8.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. z For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
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29.8.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 29-3 shows signal multiplexing depending on the data bus width and the byte access type. For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused.
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29.9 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 29.9.
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29.9.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles.
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29.9.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 29.9.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first.
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Figure 29-11.READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS tPACC D[31:0] Data Sampling 29.9.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 29-12. The write cycle starts with the address setting on the memory address bus. 29.9.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1.
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Figure 29-12.Write Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NWE_SETUP NCS_WR_SETUP NWE_PULSE NWE_HOLD NCS_WR_PULSE NCS_WR_HOLD NWE_CYCLE 29.9.3.3 Write Cycle The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change.
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Figure 29-13.Null Setup and Hold Values of NCS and NWE in Write Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] NWE_PULSE NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE NWE_CYCLE 29.9.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 29.9.
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29.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 29-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. Figure 29-15.WRITE_MODE = 0.
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Table 29-4 shows how the timing parameters are coded and their permitted range. Table 29-4. Coding and Range of Timing Parameters Permitted Range Coded Value Number of Bits Effective Value Coded Value Effective Value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤≤31 0 ≤≤128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤≤63 0 ≤≤256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤≤127 0 ≤≤256+127 0 ≤≤512+127 0 ≤≤768+127 29.9.
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Figure 29-16.Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWE NCS0 NCS2 NRD_CYCLE NWE_CYCLE D[31:0] Read to Write Chip Select Wait State Wait State 29.10.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins.
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Figure 29-17.Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NRD no hold no setup D[31:0] write cycle Early Read wait state read cycle Figure 29-18.
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Figure 29-19.Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 internal write controlling signal external write controlling signal (NWE) no hold read setup = 1 NRD D[31:0] write cycle (WRITE_MODE = 1) Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) 29.10.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface.
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29.10.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 29-16 on page 380. 29.11 Data Float Wait States Some memory devices are slow to release the external bus.
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Figure 29-20.TDF Period in NRD Controlled Read Access (TDF = 2) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NRD NCS tpacc D[31:0] TDF = 2 clock cycles NRD controlled read operation Figure 29-21.
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29.11.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 29-22 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
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Figure 29-23.TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[31:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 29-24.
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Figure 29-25.TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[31:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 29.12 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
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29.12.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 29-26.
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Figure 29-27.
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29.12.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 29-28 and Figure 29-29. After deassertion, the access is completed: the hold step of the access is performed.
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Figure 29-29.
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29.12.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
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29.13 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
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29.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 29-32 on page 394. The external device may not be fast enough to support such timings. Figure 29-33 illustrates the recommended procedure to properly switch from one mode to the other. Figure 29-32.
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Figure 29-33.
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29.14 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
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In page mode, the programming of the read timings is described in Table 29-7: Table 29-7. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
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Figure 29-35.
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29.15 Programmable IO Delays The external bus interface consists of a data bus, an address bus and control signals. The simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, SMC_DELAY1-8. The additional programmable delays for each IO range from 0 to 4 ns (Worst Case PVT).
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29.16 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 29-8. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 29-8, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 29-8.
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29.16.1 SMC Setup Register Name: SMC_SETUP[0..
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29.16.2 SMC Pulse Register Name: SMC_PULSE[0..
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29.16.3 SMC Cycle Register Name: SMC_CYCLE[0..5] Address: 0xFFFFEA08 [0], 0xFFFFEA18 [1], 0xFFFFEA28 [2], 0xFFFFEA38 [3], 0xFFFFEA48 [4], 0xFFFFEA58 [5] Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – NRD_CYCLE 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 – – – – – – – NWE_CYCLE 7 6 5 4 3 2 1 0 NWE_CYCLE • NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle.
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29.16.4 SMC MODE Register Name: SMC_MODE[0..5] Address: 0xFFFFEA0C [0], 0xFFFFEA1C [1], 0xFFFFEA2C [2], 0xFFFFEA3C [3], 0xFFFFEA4C [4], 0xFFFFEA5C [5] Access: Read-write 31 30 – – 23 22 21 20 – – – TDF_MODE 15 14 13 12 – – 7 6 – – 29 28 PS DBW 5 4 EXNW_MODE 27 26 25 24 – – – PMEN 19 18 17 16 TDF_CYCLES 11 10 9 8 – – – BAT 3 2 1 0 – – WRITE_MODE READ_MODE • READ_MODE: 1: The read operation is controlled by the NRD signal.
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• BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
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29.16.5 SMC DELAY I/O Register Name: SMC_DELAY 1-8 Address: 0xFFFFEAC0 [1] .. 0xFFFFEADC [8] Access: Read-write Reset: See Table 29-8 31 30 29 28 27 26 Delay8 23 22 21 20 19 18 Delay6 15 14 13 6 24 17 16 9 8 1 0 Delay5 12 11 10 Delay4 7 25 Delay7 Delay3 5 Delay2 4 3 2 Delay1 • Delay x: Gives the number of elements in the delay line.
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29.16.6 SMC Write Protect Mode Register Name: SMC_WPMR Address: 0xFFFFEAE4 Access: Read-write Reset: See Table 29-8 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
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29.16.7 SMC Write Protect Status Register Name: SMC_WPSR Address: 0xFFFFEAE8 Access: Read-only Reset: See Table 29-8 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register.
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30. DDR SDR SDRAM Controller (DDRSDRC) 30.1 Description The DDR SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol. The DDRSDRC extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRSDRAM device and external 16-bit DDR-SDRAM device.
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30.
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30.3 DDRSDRC Module Diagram Figure 30-1.
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30.4 Initialization Sequence The addresses given are for example purposes only. The real address depends on implementation in the product. 30.4.1 SDR-SDRAM Initialization The initialization sequence is generated by software. The SDR-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 30.7.8 on page 448). 2. Program the features of the SDR-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.
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4. An NOP command will be issued to the low-power DDR1-SDRAM. Program NOP command into the Mode Register, the application must set Mode to 1 in the Mode Register (see Section 30.7.1 on page 437). Perform a write access to any DDR1-SDRAM address to acknowledge this command. Now clocks which drive DDR1-SDRAM device are enabled. A minimum pause of 200 μs will be provided to precede any signal toggle. 5. An all banks precharge command is issued to the low-power DDR1-SDRAM.
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6. An Extended Mode Register set (EMRS2) cycle is issued to chose between commercial or high temperature operations. The application must set Mode to 5 in the Mode Register (see Section 30.7.1 on page 437) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0.
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19. A mode Normal command is provided. Program the Normal mode into Mode Register (see Section 30.7.1 on page 437). Perform a write access to any DDR2-SDRAM address to acknowledge this command. 20. Perform a write access to any DDR2-SDRAM address. 21. Write the refresh rate into the count field in the Refresh Timer register (see page 438). (Refresh rate = delay between refresh cycles). The DDR2-SDRAM device requires a refresh every 15.625 μs or 7.81 μs.
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Figure 30-2. Single Write Access, Row Closed, Low-power DDR1-SDRAM Device SDCLK Row a A[12:0] COMMAND BA[1:0] PRCHG NOP NOP col a ACT NOP WRITE NOP 00 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da Trp = 2 3 Db Trcd = 2 Figure 30-3.
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Figure 30-4. Single Write Access, Row Closed, SDR-SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] Row a NOP PRCHG NOP ACT Col a NOP WRITE BST NOP 00 3 DM[1:0] 0 D[31:0] 3 DaDb Trp = 2 Trcd = 2 Figure 30-5.
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Figure 30-6. Burst Write Access, Row Closed, DDR2-SDRAM Device SDCLK A[12:0] Row a COMMAND BA[1:0] NOP PRCHG NOP col a ACT NOP WRITE NOP 0 DQS[1:0] DM[1:0] 3 0 D [15:0] Da Db Dc Dd 3 De Df Dg Dh Trcd = 2 Trp = 2 Figure 30-7.
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Figure 30-8. Write Command Followed By a Read Command without Burst Write Interrupt, Low-power DDR1-SDRAM Device SDCLK A[12:0] col a COMMAND NOP BA[1:0] col a WRITE NOP READ BST NOP 0 DQS[1:0] DM[1:0] 3 0 D[15:0] 3 Da Db Dc Dd De Df Dg Dh Da Db Twrd = BL/2 +2 = 8/2 +2 = 6 Twr = 1 In the case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle prior to the read command to avoid writing invalid data.
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Figure 30-10.SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] col a Row a NOP PRCHG NOP ACT NOP WRITE NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da 3 Da Db Db Data masked twtr 30.5.2 SDRAM Controller Read Cycle The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance of the DDRSDRC.
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Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given read command. When the read command is issued, 8 columns are selected. All accesses for that burst take place within these eight columns, meaning that the burst wraps within these 8 columns if the boundary is reached. These 8 columns are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block.
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Figure 30-12.Single Read Access, Row Close, Latency = 3, DDR2-SDRAM Device SDCLK A[12:0] COMMAND BA[1:0] NOP PRCHG NOP Row a Col a ACT NOP READ 0 DQS[1] DQS[0] DM[1:0] 3 D[15:0] Da Trp Db Latency = 2 Trcd Figure 30-13.
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Figure 30-14.Burst Read Access, Latency = 2, Low-power DDR1-SDRAM Devices SDCLK Col a A[12:0] COMMAND BA[1:0] NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Dc Dd De Da Db Dc Db Df Dg Dh Latency = 2 Figure 30-15.
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Figure 30-16.Burst Read Access, Latency = 2, SDR-SDRAM Devices SDCLK A[12:0] COMMAND BA[1:0] col a NOP READ NOP BST NOP 0 DQS[1:0] DM[3:0] F D[31:0] DaDb DcDd DeDf Dg Dh Latency = 2 30.5.3 Refresh (Auto-refresh Command) An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The DDRSDRC generates these auto-refresh commands periodically.
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After initialization, as soon as PASR/DS/TCSR fields are modified, the Extended Mode Register in the memory of the external device is accessed automatically and PASR/DS/TCSR bits are updated before entry into self refresh mode if DDRSDRC does not share an external bus with another controller or during a refresh command, and a pending read or write access, if DDRSDRC does share an external bus with another controller. This type of update is a function of the UPD_MR bit (see Section 30.7.
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Figure 30-18.Self Refresh Mode Entry, Timeout = 1 or 2 SDCLK A[12:0] COMMAND NOP READ BST NOP PRCHG NOP ARFSH NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db 64 or 128 wait states Trp Enter Self refresh Mode Figure 30-19.
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Figure 30-20.Self Refresh and Automatic Update SDCLK Pasr-Tcr-Ds A[12:0] COMMAND NOP PRCHG NOP MRS NOP NOP ARFSH CKE BA[1:0] 0 2 Enter Self Refresh Mode Tmrd Trp Update Extended Mode register Figure 30-21.Automatic Update During AUTO-REFRESH Command and SDRAM Access SDCLK A[12:0] COMMAND Pasr-Tcr-Ds NOP PRCHALL NOP ARFSH NOP MRS NOP ACT CKE BA[1:0] 0 0 2 Trp Trfc Tmrd Update Extended mode register 30.5.4.
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z 00 = Power-down mode is enabled as soon as the SDRAM device is not selected z 01 = Power-down mode is enabled 64 clock cycles after completion of the last access z 10 = Power-down mode is enabled 128 clock cycles after completion of the last access Figure 30-22.Power-down Entry/Exit, Timeout = 0 SDCLK A[12:0] COMMAND READ BST NOP READ CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Exit power down mode Entry power down mode 30.5.4.
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30.5.4.4 Reset Mode The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-power command bits (LPCB) to 11 and the clock frozen command bit (CLK_FR) to 1. When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. Before enabling this mode, the end user must assume there is not an access in progress.
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The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the SDRAM device at the same time. The arbitration type is round-robin arbitration. This algorithm dispatches the requests from different masters to the SDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is serviced first, then the others are serviced in a round-robin manner.
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30.5.6 Write Protected Registers To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be writeprotected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
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30.6 Software Interface/SDRAM Organization, Address Mapping The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps different memory types depending on the values set in the DDRSDRC Configuration Register. See Section 30.7.3 “DDRSDRC Configuration Register” on page 439. The following figures illustrate the relation between CPU addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths.
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Table 30-4. Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 Bk[1:0] 17 16 15 14 13 12 11 10 9 8 7 Row[13:0] Bk[1:0] 5 4 3 2 1 M0 Column[9:0] Row[13:0] 0 M0 Column[8:0] Row[13:0] Bk[1:0] 6 M0 Column[10:0] Table 30-5.
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Table 30-8. Interleaved Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[13:0] 11 10 9 8 7 Bk[1:0] Row[13:0] 5 4 3 2 1 M0 Column[9:0] Bk[1:0] 0 M0 Column[8:0] Bk[1:0] Row[13:0] 6 M0 Column[10:0] 30.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks Table 30-9.
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Table 30-13. SDR-SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 Bk[1:0] 16 15 14 13 12 11 10 9 8 Row[10:0] Bk[1:0] 6 5 4 3 2 Column[8:0] Row[10:0] Bk[1:0] 7 0 M[1:0] Column[9:0] Row[10:0] 1 M[1:0] Column[10:0] M[1:0] Table 30-14.
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30.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface The User Interface is connected to the APB bus. The DDRSDRC is programmed using the registers listed in Table 30-16 Table 30-16.
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30.7.1 DDRSDRC Mode Register Name: DDRSDRC_MR Address: 0xFFFFE800 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – MODE This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 451.
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30.7.2 DDRSDRC Refresh Timer Register Name: DDRSDRC_RTR Address: 0xFFFFE804 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – 7 6 5 4 1 0 COUNT 3 2 COUNT This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 451.
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30.7.3 DDRSDRC Configuration Register Name: DDRSDRC_CR Address: 0xFFFFE808 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – DECOD – NB – ACTBST – EBISHARE 15 14 13 12 11 10 9 8 – – DIS_DLL DIC/DS 2 1 – 7 OCD 6 5 DLL 4 3 CAS NR 0 NC This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 451.
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CAS DDR2 CAS Latency SDR CAS Latency 011 3 3 100 Reserved Reserved 101 Reserved Reserved 110 Reserved Reserved 111 Reserved Reserved • DLL: Reset DLL Reset value is 0. This field defines the value of Reset DLL. 0 = Disable DLL reset. 1 = Enable DLL reset. This value is used during the power-up sequence. Note: Note: This field is found only in DDR2-SDRAM devices. • DIC/DS: Output Driver Impedance Control Reset value is 0. This field defines the output drive strength.
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• ACTBST: ACTIVE Bank X to Burst Stop Read Access Bank Y Reset value is 0. 0 = After an ACTIVE command in Bank X, BURST STOP command can be issued to another bank to stop current read access. 1 = After an ACTIVE command in Bank X, BURST STOP command cannot be issued to another bank to stop current read access. This field is unique to SDR-SDRAM, Low-power SDR-SDRAM and Low-power DDR1-SDRAM devices. • NB: Number of Banks The reset value is four banks.
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30.7.4 DDRSDRC Timing Parameter 0 Register Name: DDRSDRC_TPR0 Address: 0xFFFFE80C Access: Read-write Reset: See Table 30-16 31 30 29 28 TMRD 23 22 27 26 21 20 19 14 18 13 6 17 16 9 8 1 0 TRP 12 11 10 TRC 7 24 TWTR TRRD 15 25 REDUCE_WRRD TWR 5 TRCD 4 3 2 TRAS This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 451. • TRAS: Active to Precharge Delay Reset Value is 5 cycles.
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• TWTR: Internal Write to Read Delay Reset value is 0. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices. This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 7. • REDUCE_WRRD: Reduce Write to Read Delay Reset value is 0. This field reduces the delay between write to read access for low-power DDR-SDRAM devices with a latency equal to 2. To use this feature, TWTR field must be equal to 0.
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30.7.5 DDRSDRC Timing Parameter 1 Register Name: DDRSDRC_TPR1 Address: 0xFFFFE810 Access: Read-write Reset: See Table 30-16 31 30 29 28 – – – – 23 22 21 20 27 26 25 24 TXP 19 18 17 16 11 10 9 8 2 1 0 TXSRD 15 14 13 12 TXSNR 7 6 5 – – – 4 3 TRFC This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 451. • TRFC: Row Cycle Delay Reset Value is 8 cycles.
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30.7.6 DDRSDRC Timing Parameter 2 Register Name: DDRSDRC_TPR2 Address: 0xFFFFE814 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 9 8 1 0 TFAW 11 10 TRTP 7 6 5 TRPA 4 3 2 TXARDS TXARD This register can only be written if the WPEN bit is cleared in “DDRSDRC Write Protect Mode Register” on page 451. • TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”.
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30.7.7 DDRSDRC Low-power Register Name: DDRSDRC_LPR Address: 0xFFFFE81C Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – APDE 15 14 11 10 9 8 – – 7 6 – UPD_MR 13 12 TIMEOUT 5 – 4 PASR 3 DS 2 CLK_FR 1 0 LPCB • LPCB: Low-power Command Bit Reset value is “00”. 00 = Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
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After the initialization sequence, as soon as DS field is modified, Extended Mode Register is accessed automatically and DS bits are updated. In function of UPD_MR bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access. • TIMEOUT: Low Power Mode Reset value is “00”. This field defines when low-power mode is enabled. 00 The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.
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30.7.8 DDRSDRC Memory Device Register Name: DDRSDRC_MD Address: 0xFFFFE820 Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – DBW – MD This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 451. • MD: Memory Device Indicates the type of memory used.
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30.7.9 DDRSDRC DLL Register Name: DDRSDRC_DLL Address: 0xFFFFE824 Access: Read-only Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 MDVAL 7 6 5 4 3 2 1 0 – – – – – MDOVF MDDEC MDINC The DLL logic is internally used by the controller in order to delay DQS inputs. This is necessary to center the strobe time and the data valid window.
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30.7.10 DDRSDRC High Speed Register Name: DDRSDRC_HS Address: 0xFFFFE82C Access: Read-write Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – DIS_ANTICIP_RE AD – – – – – – This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 451.
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30.7.11 DDRSDRC Write Protect Mode Register Name: DDRSDRC_WPMR Address: 0xFFFFE8E4 Access: Read-write Reset See Table 30-16 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
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30.7.12 DDRSDRC Write Protect Status Register Name: DDRSDRC_WPSR Address: 0xFFFFE8E8 Access: Read-only Reset: See Table 30-16 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DDRSDRC_WPSR register.
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31. DMA Controller (DMAC) 31.1 Description The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer.
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31.2.1 DMA Controller 0 z Two Masters z Embeds 8 channels z 64-byte FIFO for channel 0, 16-byte FIFO for Channel 1 to 7 z Features: z Linked List support with Status Write Back operation at End of Transfer z Word, HalfWord, Byte transfer support. z Memory to memory transfer z Peripheral to memory z Memory to peripheral The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals below.
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31.2.2 DMA Controller 1 z Two Masters z Embeds 8 channels z 16-byte FIFO per Channel z Features: z Linked List support with Status Write Back operation at End of Transfer z Word, HalfWord, Byte transfer support. z Peripheral to memory z Memory to peripheral The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals below. The hardware interface numbers are also given in Table 31-2. Table 31-2.
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31.3 Block Diagram Figure 31-1.
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31.4 Functional Description 31.4.1 Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
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Figure 31-2. DMAC Transfer Hierarchy for Non-Memory Peripheral DMAC Transfer Buffer Buffer Chunk Transfer AMBA Burst Transfer DMA Transfer Level Buffer Transfer Level Buffer Chunk Transfer Chunk Transfer AMBA Single Transfer AMBA Burst Transfer AMBA Burst Transfer Single Transfer DMA Transaction Level AMBA Single Transfer AMBA Transfer Level Figure 31-3.
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Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. The source and destination can independently select which method to use. z Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory where the next linked list item (LLI) exists.
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31.4.2 Memory Peripherals Figure 31-3 on page 458 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled.
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31.4.4 DMAC Transfer Types A DMAC transfer may consist of single or multi-buffer transfers.
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31.4.4.2 Programming DMAC for Multiple Buffer Transfers Table 31-3.
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Replay Mode of Channel Registers During automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer and the new values used for the new buffer. Depending on the row number in Figure 31-1 on page 456, some or all of the DMAC_SADDRx, DMAC_DADDRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their initial value at the start of a buffer transfer.
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5. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers for channel x. For example, in the register, you can program the following: z i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. z ii. Set up the transfer characteristics, such as: z Transfer width for the source in the SRC_WIDTH field.
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3. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel.
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transfer match described in Row 1 of Table 31-3 on page 462. The DMAC then knows that the previous buffer transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 31-6 on page 466. Figure 31-6.
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The DMAC transfer flow is shown in Figure 31-8 on page 467. Figure 31-8.
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Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10) 1. Read the Channel Handler Status register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. Program the following channel registers: 1. Write the starting source address in the DMAC_SADDRx register for channel x. 2.
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6. The DMAC transfer proceeds as follows: 1. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has completed. It then stalls until the STALx bit of DMAC_CHSR register is cleared by software, writing ‘1’ to DMAC_CHER.KEEPx bit, where x is the channel number.
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Figure 31-10.
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4. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel.
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Buffer Transfer Completed Interrupt, or poll for the Channel Enable. (DMAC_CHSR.ENAx) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 31-3 on page 462, the following step is performed. 19. The DMAC fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers.
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Figure 31-12.
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z Incrementing/decrementing or fixed address for source in SRC_INCR field. z Incrementing/decrementing or fixed address for destination in DST_INCR field. 5. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 6. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. 7. Write the channel configuration information into the DMAC_CFGx register for channel x. z i.
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Figure 31-13.
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Figure 31-14.
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3. Note: 4. Write the starting destination address in the DMAC_DADDRx register for channel x. The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. Write the channel configuration information into the DMAC_CFGx register for channel x. 1. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory.
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18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, then automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register is left unchanged.
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Figure 31-16.DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address Channel enabled by software LLI Fetch Hardware reprograms SADDRx, CTRLAx,CTRLBx, DSCRx DMAC buffer transfer Writeback of control information of LLI Buffer Transfer Completed Interrupt generated here Is DMAC in Row 1 ? DMAC Chained Buffer Transfer Completed Interrupt generated here no yes Channel disabled by hardware 31.4.
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1. If the software wishes to disable a channel n prior to the DMAC transfer completion, then it can set the DMAC_CHER.SUSPx bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel FIFO receives no new data. 2. The software can now poll the DMAC_CHSR.EMPTx bit until it indicates that the channel n FIFO is empty, where n is the channel number. 3. The DMAC_CHER.ENAx bit can then be cleared by software once the channel n FIFO is empty, where n is the channel number.
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31.5 DMAC Software Requirements z There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel. z When the destination peripheral has been defined as the flow controller, source single transfer requests are not serviced until the destination peripheral has asserted its Last Transfer Flag.
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31.6 Write Protection Registers To prevent any single software error that may corrupt the DMAC behavior, the DMAC address space can be writeprotected by setting the WPEN bit in the “DMAC Write Protect Mode Register” (DMAC_WPMR). If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the DMAC Write Protect Status Register (MCI_WPSR) is set, and the WPVSRC field indicates in which register the write access has been attempted.
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31.7 DMA Controller (DMAC) User Interface Table 31-4.
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31.7.1 DMAC Global Configuration Register Name: DMAC_GCFG Address: 0xFFFFEC00 (0), 0xFFFFEE00 (1) Access: Read-write Reset: 0x00000010 Note: 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ARB_CFG 3 – 2 – 1 – 0 – Bit fields 0, 1, 2, 3, have a default value of 0. This should not be changed.
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31.7.2 DMAC Enable Register Name: DMAC_EN Address: 0xFFFFEC04 (0), 0xFFFFEE04 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 ENABLE This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” . • ENABLE: General Enable of DMA 0: DMA Controller is disabled. 1: DMA Controller is enabled.
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31.7.3 DMAC Software Single Request Register Name: DMAC_SREQ Address: 0xFFFFEC08 (0), 0xFFFFEE08 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DSREQ7 14 SSREQ7 13 DSREQ6 12 SSREQ6 11 DSREQ5 10 SSREQ5 9 DSREQ4 8 SSREQ4 7 DSREQ3 6 SSREQ3 5 DSREQ2 4 SSREQ2 3 DSREQ1 2 SSREQ1 1 DSREQ0 0 SSREQ0 • DSREQx: Destination Request Request a destination single transfer on channel i.
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31.7.4 DMAC Software Chunk Transfer Request Register Name: DMAC_CREQ Address: 0xFFFFEC0C (0), 0xFFFFEE0C (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 DCREQ7 14 SCREQ7 13 DCREQ6 12 SCREQ6 11 DCREQ5 10 SCREQ5 9 DCREQ4 8 SCREQ4 7 DCREQ3 6 SCREQ3 5 DCREQ2 4 SCREQ2 3 DCREQ1 2 SCREQ1 1 DCREQ0 0 SCREQ0 • DCREQx: Destination Chunk Request Request a destination chunk transfer on channel i.
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31.7.
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31.7.
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31.7.
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31.7.
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31.7.
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31.7.10 DMAC Channel Handler Enable Register Name: DMAC_CHER Address: 0xFFFFEC28 (0), 0xFFFFEE28 (1) Access: Write-only Reset: 0x00000000 31 KEEP7 30 KEEP6 29 KEEP5 28 KEEP4 27 KEEP3 26 KEEP2 25 KEEP1 24 KEEP0 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SUSP7 14 SUSP6 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 ENA7 6 ENA6 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 • ENAx: Enable [7:0] When set, a bit of the ENA field enables the relevant channel.
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31.7.11 DMAC Channel Handler Disable Register Name: DMAC_CHDR Address: 0xFFFFEC2C (0), 0xFFFFEE2C (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RES7 14 RES6 13 RES5 12 RES4 11 RES3 10 RES2 9 RES1 8 RES0 7 DIS7 6 DIS6 5 DIS5 4 DIS4 3 DIS3 2 DIS2 1 DIS1 0 DIS0 • DISx: Disable [7:0] Write one to this field to disable the relevant DMAC Channel.
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31.7.
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31.7.13 DMAC Channel x [x = 0..7] Source Address Register Name: DMAC_SADDRx [x = 0..
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31.7.14 DMAC Channel x [x = 0..7] Destination Address Register Name: DMAC_DADDRx [x = 0..
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31.7.15 DMAC Channel x [x = 0..7] Descriptor Address Register Name: DMAC_DSCRx [x = 0..
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31.7.16 DMAC Channel x [x = 0..7] Control A Register Name: DMAC_CTRLAx [x = 0..
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• SRC_WIDTH: Transfer Width for the Source Value Name Description 00 BYTE the transfer size is set to 8-bit width 01 HALF_WORD the transfer size is set to 16-bit width 1X WORD the transfer size is set to 32-bit width • DST_WIDTH: Transfer Width for the Destination Value Name Description 00 BYTE the transfer size is set to 8-bit width 01 HALF_WORD the transfer size is set to 16-bit width 1X WORD the transfer size is set to 32-bit width • DONE: Current Descriptor Stop Command and Trans
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31.7.17 DMAC Channel x [x = 0..7] Control B Register Name: DMAC_CTRLBx [x = 0..
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• DST_DSCR: Destination Address Descriptor 0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination. • FC: Flow Control This field defines which device controls the size of the buffer transfer, also referred to as the Flow Controller.
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31.7.18 DMAC Channel x [x = 0..7] Configuration Register Name: DMAC_CFGx [x = 0..
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• SOD: Stop On Done 0 (DISABLE): STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 (ENABLE): STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. • LOCK_IF: Interface Lock 0 (DISABLE): Interface Lock capability is disabled 1 (ENABLE): Interface Lock capability is enabled • LOCK_B: Bus Lock 0 (DISABLE): AHB Bus Locking capability is disabled. 1(ENABLE): AHB Bus Locking capability is enabled.
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31.7.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register Name: DMAC_SPIPx [x = 0..
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31.7.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register Name: DMAC_DPIPx [x = 0..
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31.7.21 DMAC Write Protect Mode Register Name: DMAC_WPMR Address: 0xFFFFEDE4 (0), 0xFFFFEFE4 (1) Access: Read-write Reset: See Table 31-4 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444D41 (“DMA” in ASCII).
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31.7.22 DMAC Write Protect Status Register Name: DMAC_WPSR Address: 0xFFFFEDE8 (0), 0xFFFFEFE8 (1) Access: Read-only Reset: See Table 31-4 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DMAC_WPSR register.
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32. USB High Speed Device Port (UDPHS) 32.1 Description The USB High Speed Device Port (UDPHS) is compliant with the Universal Serial Bus (USB), rev 2.0 High Speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a Dual-port RAM used to store the current data payload.
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32.3 Block Diagram Figure 32-1. Block Diagram APB Interface APB bus ctrl status DHSDP DHSDM AHB1 AHB bus Rd/Wr/Ready DMA AHB0 AHB bus UTMI USB2.
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32.4 Typical Connection Figure 32-2. Board Schematic PIO (VBUS DETECT) 15k Ω (1) "B" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND 1 DHSDM 39 ± 1% Ω DFSDM 2 Shell = Shield (1) 22k Ω CRPB 3 DHSDP 4 39 ± 1% Ω CRPB:1µF to 10µF DFSDP 6K8 ± 1% Ω VBG 10 pF GNDUTMI Note: 32.5 The values shown on the 22 kΩ and 15 kΩ resistors are only valid with 3V3 supplied PIOs. Both 39 Ω resistors need to be placed as close to the device pins as possible. Product Dependencies 32.5.
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32.6 Functional Description 32.6.1 UTMI Transceivers Sharing The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second UTMI transceiver. The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register. Figure 32-3. USB Selection Other Transceivers HS Transceiver EN_UDPHS 0 Others Ports 1 PA HS USB Host HS EHCI FS OHCI DMA HS USB Device DMA 32.6.2 USB V2.
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32.6.4 USB Transfer Event Definitions A transfer is composed of one or several transactions; Table 32-3.
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Figure 32-4. Control Read and Write Sequences Setup Stage Control Write Setup TX Data Stage Data OUT TX Setup Stage Control Read No Data Control Setup TX Status Stage Status IN TX Data OUT TX Data Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Status Stage Data IN TX Status OUT TX A status IN or OUT transaction is identical to a data IN or OUT transaction. 32.6.
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The size of the DPRAM is 4 KB. The DPR is shared by all active endpoints. The memory size required by the active endpoints must not exceed the size of the DPRAM. SIZE_DPRAM = SIZE _EPT0 + NB_BANK_EPT1 x SIZE_EPT1 + NB_BANK_EPT2 x SIZE_EPT2 + NB_BANK_EPT3 x SIZE_EPT3 + NB_BANK_EPT4 x SIZE_EPT4 + NB_BANK_EPT5 x SIZE_EPT5 + NB_BANK_EPT6 x SIZE_EPT6 +... (refer to 32.7.
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Configuration examples of UDPHS_EPTCTLx (UDPHS Endpoint Control Disable Register (Isochronous Endpoint)) for Bulk IN endpoint type follow below. z z With DMA z AUTO_VALID: Automatically validate the packet and switch to the next bank. z EPT_ENABL: Enable endpoint. Without DMA: z TXRDY: An interrupt is generated after each transmission. z EPT_ENABL: Enable endpoint. Configuration examples of Bulk OUT endpoint type follow below.
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Figure 32-6. Allocation and Reorganization of the DPRAM Free Memory Free Memory Free Memory EPT5 EPT5 EPT5 Free Memory EPT5 Conflict EPT4 EPT4 EPT4 EPT3 EPT3 (always allocated) EPT4 EPT2 EPT2 EPT2 EPT2 EPT1 EPT1 EPT1 EPT1 EPT0 EPT0 EPT0 Device: Device: EPT4 Lost Memory Device: Endpoint 3 Disabled EPT0 Device: UDPHS_EPTCTLENBx.EPT_ENABL = 1 UDPHS_EPTCTLDIS3.EPT_DISABL = 1 UDPHS_EPTCFG3.BK_NUMBER = 0 UDPHS_EPTCFGx.BK_NUMBER <> 0 Endpoints 0..
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32.6.8 Transfer With DMA USB packets of any length may be transferred when required by the UDPHS Device. These transfers always feature sequential addressing. Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance boost with paged memories.
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for( i=1; i<=((AT91C_BASE_UDPHS->UDPHS_IPFEATURES & AT91C_UDPHS_DMA_CHANNEL_NBR)>>4); i++ ) { // RESET endpoint canal DMA: // DMA stop channel command AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Disable endpoint AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLDIS |= 0XFFFFFFFF; // Reset endpoint config AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLCFG = 0; // Reset DMA channel (Buff count and Control field) AT91C_BASE_UDPHS->UDPHS_DMA[i].
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Figure 32-8. NYET Example with Two Endpoint Banks data 0 ACK t=0 data 1 NYET t = 125 μs Bank 1 E Bank 0 F PING ACK t = 250 μs Bank 1 F Bank 1 F Bank 0 E' Bank 0 E data 0 NYET t = 375 μs Bank 1 F Bank 0 E PING t = 500 μs Bank 1 F Bank 0 F NACK PING t = 625 μs Bank 1 E' Bank 0 F ACK E: empty E': begin to empty F: full Bank 1 E Bank 0 F 32.6.10.3 Data IN 32.6.10.
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32.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer types except control transfer. Example DMA configuration: 1. Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred. 2. Enable the interrupt of the DMA in UDPHS_IEN 3.
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Figure 32-9.
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Figure 32-11.Data IN Followed By Status OUT Transfer at the End of a Control Transfer Device Sends the Last Data Payload to Host USB Bus Packets Token IN Device Sends a Status OUT to Host ACK Data IN Token OUT Data OUT (ZLP) ACK Token OUT ACK Data OUT (ZLP) Interrupt Pending RXRDY (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware TX_COMPLT (UDPHS_EPTSTAx) Set by Hardware Note: Cleared by Firmware A NAK handshake is always generated at the first status stage token. Figure 32-12.
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Figure 32-13.Autovalid with DMA Bank (system) Write Bank 0 Bank 1 write bank 0 write bank 1 bank 0 is full Bank 1 Bank 0 Bank 1 write bank 0 bank 1 is full bank 0 is full Bank 0 IN data 0 Bank (usb) Bank 0 IN data 0 IN data 1 Bank 0 Bank 1 Bank 1 Virtual TXRDY Bank 0 Virtual TXRDY Bank 1 TXRDY (Virtual 0 & Virtual 1) Note: In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing data and to send to DMA. 32.6.
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z If no bank is validated yet, the default DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). Then, no data bank is flushed at microframe end. z If no data bank has been validated at the time when a response should be made for the second transaction of NB_TRANS = 3 transactions microframe, a DATA1 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx).
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Algorithm to Fill Several Packets: z The application enables the interrupts of BUSY_BANK and AUTO_VALID. z When a BUSY_BANK interrupt is received, the application knows that all banks available for the endpoint have been filled. Thus, the application can read all banks available. If the application doesn’t know the size of the receive buffer, instead of using the BUSY_BANK interrupt, the application must use RXRDY_TXKL. 32.6.10.
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Figure 32-15.
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z z If NB_TRANS = 2, the sequence should be either z MData0 z MData0/Data1 If NB_TRANS = 1, the sequence should be z Data0 32.6.10.14 Isochronous Endpoint Handling: OUT Example The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the UDPHS_EPTSTAx register in the three bit fields as follows: z TOGGLESQ_STA: PID of the data stored in the current bank z CURBK: Number of the bank currently being accessed by the microcontroller.
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Figure 32-18.Stall Handshake Data IN Transfer USB Bus Packets Token IN Stall PID FRCESTALL Cleared by Firmware Set by Firmware Interrupt Pending STALL_SNT Set by Hardware Cleared by Firmware 32.6.11 Speed Identification The high speed reset is managed by the hardware. At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. At the end of the reset process (full or high), the ENDRESET interrupt is generated.
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Figure 32-19.
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32.6.14 Power Modes 32.6.14.1 Controlling Device States A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus Specification, Rev 2.0. Figure 32-20.
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32.6.14.2 Not Powered State Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a host, device power consumption can be reduced by the DETACH bit in UDPHS_CTRL. Disabling the transceiver is automatically done. HSDM, HSDP, FSDP and FSDP lines are tied to GND pull-downs integrated in the hub downstream ports. 32.6.14.
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32.6.14.8 Receiving a Host Resume In Suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks disabled (however the pull-up should not be removed). Once the resume is detected on the bus, the signal WAKE_UP in the UDPHS_INTSTA is set. It may generate an interrupt if the corresponding bit in the UDPHS_IEN register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. 32.6.14.
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32.7 USB High Speed Device Port (UDPHS) User Interface Table 32-6.
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32.7.
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(See DETACH description above.
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32.7.2 UDPHS Frame Number Register Name: UDPHS_FNUM Address: 0xF803C004 Access: Read-only 31 FNUM_ERR 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 FRAME_NUMBER 9 8 7 6 5 FRAME_NUMBER 4 3 1 MICRO_FRAME_NUM 0 2 • MICRO_FRAME_NUM: Microframe Number Number of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1 ms). One microframe is received each 125 microseconds (1 ms/8).
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32.7.3 UDPHS Interrupt Enable Register Name: UDPHS_IEN Address: 0xF803C010 Access: Read-write 31 – 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Enable 0 = Disable Suspend Interrupt. 1 = Enable Suspend Interrupt.
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• DMA_x: DMA Channel x Interrupt Enable 0 = Disable the interrupts for this channel. 1 = Enable the interrupts for this channel.
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32.7.4 UDPHS Interrupt Status Register Name: UDPHS_INTSTA Address: 0xF803C014 Access: Read-only 31 – 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 SPEED • SPEED: Speed Status 0 = Reset by hardware when the hardware is in Full Speed mode.
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• WAKE_UP: Wake Up CPU Interrupt 0 = Cleared by setting the WAKE_UP bit in UDPHS_CLRINT. 1 = Set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation.
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32.7.5 UDPHS Clear Interrupt Register Name: UDPHS_CLRINT Address: 0xF803C018 Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Clear 0 = No effect. 1 = Clear the DET_SUSPD bit in UDPHS_INTSTA. • MICRO_SOF: Micro Start Of Frame Interrupt Clear 0 = No effect.
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32.7.6 UDPHS Endpoints Reset Register Name: UDPHS_EPTRST Address: 0xF803C01C Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 EPT_6 5 EPT_5 4 EPT_4 3 EPT_3 2 EPT_2 1 EPT_1 0 EPT_0 • EPT_x: Endpoint x Reset 0 = No effect. 1 = Reset the Endpointx state. Setting this bit clears the Endpoint status UDPHS_EPTSTAx register, except for the TOGGLESQ_STA field.
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32.7.
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Upon command, a port’s transceiver must enter the High Speed receive mode and remain in that mode until the exit action is taken. This enables the testing of output impedance, low level output voltage and loading characteristics. In addition, while in this mode, upstream facing ports (and only upstream facing ports) must respond to any IN token packet with a NAK handshake (only if the packet CRC is determined to be correct) within the normal allowed device response time.
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32.7.8 UDPHS Endpoint Configuration Register Name: UDPHS_EPTCFGx [x=0..
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Endpoint Type Value Name Description 0 CTRL8 Control endpoint 1 ISO Isochronous endpoint 2 BULK Bulk endpoint 3 INT Interrupt endpoint • BK_NUMBER: Number of Banks Set this field according to the endpoint’s number of banks (see Section 32.6.6 ”Endpoint Configuration”).
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32.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLENBx [x=0..
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• TXRDY: TX Packet Ready Interrupt Enable 0 = No effect. 1 = Enable TX Packet Ready/Transaction Error Interrupt. • RX_SETUP: Received SETUP 0 = No effect. 1 = Enable RX_SETUP Interrupt. • STALL_SNT: Stall Sent Interrupt Enable 0 = No effect. 1 = Enable Stall Sent Interrupt. • NAK_IN: NAKIN Interrupt Enable 0 = No effect. 1 = Enable NAKIN Interrupt. • NAK_OUT: NAKOUT Interrupt Enable 0 = No effect. 1 = Enable NAKOUT Interrupt. • BUSY_BANK: Busy Bank Interrupt Enable 0 = No effect.
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32.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints) Name: UDPHS_EPTCTLENBx [x=0..
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• TX_COMPLT: Transmitted IN Data Complete Interrupt Enable 0 = No effect. 1 = Enable Transmitted IN Data Complete Interrupt. • TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Enable 0 = No effect. 1 = Enable TX Packet Ready/Transaction Error Interrupt. • ERR_FL_ISO: Error Flow Interrupt Enable 0 = No effect. 1 = Enable Error Flow ISO Interrupt. • ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enable 0 = No effect. 1 = Enable Error CRC ISO/Error Number of Transaction Interrupt.
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32.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLDISx [x=0..
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• TXRDY: TX Packet Ready Interrupt Disable 0 = No effect. 1 = Disable TX Packet Ready/Transaction Error Interrupt. • RX_SETUP: Received SETUP Interrupt Disable 0 = No effect. 1 = Disable RX_SETUP Interrupt. • STALL_SNT: Stall Sent Interrupt Disable 0 = No effect. 1 = Disable Stall Sent Interrupt. • NAK_IN: NAKIN Interrupt Disable 0 = No effect. 1 = Disable NAKIN Interrupt. • NAK_OUT: NAKOUT Interrupt Disable 0 = No effect. 1 = Disable NAKOUT Interrupt.
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32.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint) Name: UDPHS_EPTCTLDISx [x=0..
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• TX_COMPLT: Transmitted IN Data Complete Interrupt Disable 0 = No effect. 1 = Disable Transmitted IN Data Complete Interrupt. • TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Disable 0 = No effect. 1 = Disable TX Packet Ready/Transaction Error Interrupt. • ERR_FL_ISO: Error Flow Interrupt Disable 0 = No effect. 1 = Disable Error Flow ISO Interrupt. • ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Disable 0 = No effect.
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32.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLx [x=0..
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• NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints) 0 = If cleared, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 = If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. Note: According to the Universal Serial Bus Specification, Rev 2.0 (8.5.1.1 NAK Responses to OUT/DATA During PING Protocol), a NAK response to an HS Bulk OUT transfer is expected to be an unusual occurrence.
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• SHRT_PCKT: Short Packet Interrupt Enabled For OUT endpoints: send an Interrupt when a Short Packet has been received. 0 = Short Packet Interrupt is masked. 1 = Short Packet Interrupt is enabled. For IN endpoints: a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling a BULK or INTERRUPT end of transfer, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set.
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32.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint) Name: UDPHS_EPTCTLx [x=0..
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If the exception raised is not associated to a new system bank packet (ex:ERR_FL_ISO), then the request cancellation may happen at any time and may immediately stop the current DMA transfer. This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate.
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• BUSY_BANK: Busy Bank Interrupt Enabled 0 = BUSY_BANK Interrupt is masked. 1 = BUSY_BANK Interrupt is enabled. For OUT endpoints: An interrupt is sent when all banks are busy. For IN endpoints: An interrupt is sent when all banks are free. • SHRT_PCKT: Short Packet Interrupt Enabled For OUT endpoints: send an Interrupt when a Short Packet has been received. 0 = Short Packet Interrupt is masked. 1 = Short Packet Interrupt is enabled.
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32.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTSETSTAx [x=0..
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32.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint) Name: UDPHS_EPTSETSTAx [x=0..
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32.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCLRSTAx [x=0..
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• NAK_OUT: NAKOUT Clear 0 = No effect. 1 = Clear the NAK_OUT flag of UDPHS_EPTSTAx. 32.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint) Name: UDPHS_EPTCLRSTAx [x=0..
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• ERR_FLUSH: Bank Flush Error Clear 0 = No effect. 1 = Clear the ERR_FLUSH flags of UDPHS_EPTSTAx. 32.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTSTAx [x=0..
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• ERR_OVFLW: Overflow Error This bit is set by hardware when a new too-long packet is received. Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
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• NAK_IN: NAK IN This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host. This bit is cleared by software. • NAK_OUT: NAK OUT This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
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• SHRT_PCKT: Short Packet An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
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32.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint) Name: UDPHS_EPTSTAx [x=0..
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• RXRDY_TXKL: Received OUT Data/KILL Bank – Received OUT Data (for OUT endpoint or Control endpoint): This bit is set by hardware after a new packet has been stored in the endpoint FIFO. This bit is cleared by the device firmware after reading the OUT data from the endpoint. For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile.
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• ERR_CRC_NTR: CRC ISO Error/Number of Transaction Error – CRC ISO Error (for Isochronous OUT endpoints) (Read-only): This bit is set by hardware if the last received data is corrupted (CRC error on data). This bit is updated by hardware when new data is received (Received OUT Data bit).
PAGE 573
• SHRT_PCKT: Short Packet An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
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32.7.21 UDPHS DMA Channel Transfer Descriptor The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer.
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32.7.22 UDPHS DMA Next Descriptor Address Register Name: UDPHS_DMANXTDSCx [x = 0..5] Address: 0xF803C300 [0], 0xF803C310 [1], 0xF803C320 [2], 0xF803C330 [3], 0xF803C340 [4], 0xF803C350 [5] Access: Read-write 31 30 29 28 27 NXT_DSC_ADD 26 25 24 23 22 21 20 19 NXT_DSC_ADD 18 17 16 15 14 13 12 11 NXT_DSC_ADD 10 9 8 7 6 5 4 3 NXT_DSC_ADD 2 1 0 Note: Channel 0 is not used. • NXT_DSC_ADD: Next Descriptor Address This field points to the next channel descriptor to be processed.
PAGE 576
32.7.23 UDPHS DMA Channel Address Register Name: UDPHS_DMAADDRESSx [x = 0..5] Address: 0xF803C304 [0], 0xF803C314 [1], 0xF803C324 [2], 0xF803C334 [3], 0xF803C344 [4], 0xF803C354 [5] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUFF_ADD 23 22 21 20 BUFF_ADD 15 14 13 12 BUFF_ADD 7 6 5 4 BUFF_ADD Note: Channel 0 is not used. • BUFF_ADD: Buffer Address This field determines the AHB bus starting address of a DMA channel transfer.
PAGE 577
32.7.24 UDPHS DMA Channel Control Register Name: UDPHS_DMACONTROLx [x = 0..5] Address: 0xF803C308 [0], 0xF803C318 [1], 0xF803C328 [2], 0xF803C338 [3], 0xF803C348 [4], 0xF803C358 [5] Access: Read-write 31 30 29 28 27 BUFF_LENGTH 26 25 24 23 22 21 20 19 BUFF_LENGTH 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 BURST_LCK 6 DESC_LD_IT 5 END_BUFFIT 4 END_TR_IT 3 END_B_EN 2 END_TR_EN 1 LDNXT_DSC 0 CHANN_ENB Note: Channel 0 is not used.
PAGE 578
• END_TR_EN: End of Transfer Enable (Control) Used for OUT transfers only. 0 = USB end of transfer is ignored. 1 = UDPHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close the current buffer and the UDPHS_DMASTATUSx register END_TR_ST flag will be raised. This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure.
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32.7.25 UDPHS DMA Channel Status Register Name: UDPHS_DMASTATUSx [x = 0..5] Address: 0xF803C30C [0], 0xF803C31C [1], 0xF803C32C [2], 0xF803C33C [3], 0xF803C34C [4], 0xF803C35C [5] Access: Read-write 31 30 29 28 27 BUFF_COUNT 26 25 24 23 22 21 20 19 BUFF_COUNT 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 DESC_LDST 5 END_BF_ST 4 END_TR_ST 3 – 2 – 1 CHANN_ACT 0 CHANN_ENB Note: Channel 0 is not used.
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• DESC_LDST: Descriptor Loaded Status 0 = Cleared automatically when read by software. 1 = Set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
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33. USB Host High Speed Port (UHPHS) 33.1 Description The USB Host High Speed Port (UHPHS) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as Enhanced HCI protocol (Enhanced Host Controller Interface). 33.2 Embedded Characteristics z z Compliant with Enhanced HCI Rev 1.0 Specification z Compliant with USB V2.0 High-speed z Supports High-speed 480 Mbps Compliant with OpenHCI Rev 1.0 Specification z Compliant with USB V2.
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33.3 Block Diagram Figure 33-1. Block Diagram HCI Slave Block AHB Slave OHCI Registers Root Hub Registers List Processor Block Control Embedded USB v2.
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33.4 Typical Connection Figure 33-2.
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33.5 Product Dependencies 33.5.1 I/O Lines HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High Speed physical transceivers are controlled by the USB host controller. One transceiver is shared with the USB High Speed Device (port A). The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL control register.
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Figure 33-3. UHP Clock Trees UPLL (480 MHz) 30 MHz AHB EHCI Master Interface UTMI transceiver 30 MHz USB 2.0 EHCI Host Controller Port Router EHCI User Interface UTMI transceiver FS transceiver MCK OHCI Master Interface Root Hub and Host SIE UHP48M UHP12M OHCI User Interface USB 1.1 OHCI Host Controller OHCI clocks 33.5.3 Interrupt The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
PAGE 586
Figure 33-4. USB Selection Other Transceivers HS Transceiver EN_UDPHS 0 Other Ports HS USB Host HS EHCI FS OHCI DMA 1 PA HS USB Device DMA 33.6.2 EHCI The USB Host Port controller is fully compliant with the Enhanced HCI specification. The USB Host Port User Interface (registers description) can be found in the Enhanced HCI Rev 1.0 Specification available on http://www.intel.com/technology/usb/ehcispec.htm.
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34. High Speed MultiMedia Card Interface (HSMCI) 34.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
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34.3 Block Diagram Figure 34-1. Block Diagram APB Bridge DMAC APB MCCK(1) MCCDA(1) PMC MCK MCDA0(1) HSMCI Interface PIO MCDA1(1) MCDA2(1) MCDA3(1) Interrupt Control HSMCI Interrupt 34.4 Application Block Diagram Figure 34-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc.
PAGE 589
34.5 Pin Name List Table 34-1. I/O Lines Description for 4-bit Configuration Pin Name(1) Pin Description Type(2) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0 - MCDA3 Data 0..3 of Slot A I/O/PP DAT[0..3] of an MMC DAT[0..3] of an SD Card/SDIO Notes: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. 2.
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34.6.3 Interrupt The HSMCI interface has an interrupt line connected to the interrupt controller. Handling the HSMCI interrupt requires programming the interrupt controller before configuring the HSMCI. Table 34-3. Peripheral IDs 34.7 Instance ID HSMCI0 12 HSMCI1 26 Bus Topology Figure 34-3. High Speed MultiMedia Memory Card Bus Topology 1 2 3 4 5 6 7 9 1011 1213 8 MMC The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface.
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Figure 34-4. MMC Bus Connections (One Slot) HSMCI MCDA0 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 1011 9 1011 9 1011 1213 8 MMC1 Note: 1213 8 MMC2 1213 8 MMC3 When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Figure 34-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 34-5. Table 34-5.
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MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Figure 34-6. SD Card Bus Connections with One Slot Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits.
PAGE 593
The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI Command Register. The HSMCI_CMDR allows a command to be carried out.
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The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the Interrupt Enable Register (HSMCI_IER) allows using an interrupt method. Figure 34-7.
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34.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the DMA Controller. In all cases, the block length (BLKLEN field) must be defined either in the Mode Register HSMCI_MR, or in the Block Register HSMCI_BLKR.
PAGE 596
Figure 34-8.
PAGE 597
34.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit DMAEN in the HSMCI_DMA register enables DMA transfer. The following flowchart (Figure 34-9) shows how to write a single block with or without use of DMA facilities.
PAGE 598
Figure 34-9.
PAGE 599
Figure 34-10.
PAGE 600
4. Program the HSMCI_DMA register with the following fields: z OFFSET field with dma_offset. z CHKSIZE is user defined and set according to DMAC_DCSIZE. z DMAEN is set to true to enable DMA hardware handshaking in the HSMCI. This bit was previously set to false. 5. Issue a WRITE_SINGLE_BLOCK command writing HSMCI_ARG then HSMCI_CMDR. 6. Program the DMA Controller. 1. Read the channel register to choose an available (disabled) channel. 2.
PAGE 601
5. Program HSMCI_DMA register with the following fields: z ROPT field is set to 0. z OFFSET field is set to 0. z CHKSIZE is user defined. z DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to false. 6. Issue a READ_SINGLE_BLOCK command. 7. Program the DMA controller. 1. Read the channel register to choose an available (disabled) channel. 2.
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1. Read the channel register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register. 3. Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented. This descriptor is referred to as LLI_W, standing for LLI word oriented transfer. 4. The LLI_W.DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address. 5. The LLI_W.
PAGE 603
–FC field is programmed with peripheral to memory flow control mode. –Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0. –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA Controller is able to prefetch data and write HSMCI simultaneously. 15. Program LLI_B.DMAC_CFGx memory location for Channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO.
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–SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. –Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request. 3. Wait for XFRDONE in the HSMCI_SR register. 34.8.7 WRITE_MULTIPLE_BLOCK 34.8.7.1 One Block per Descriptor 1. Wait until the current command execution has successfully terminated. 1. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR. 2.
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–DST_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_REP is set to 0. (contiguous memory access at block boundary) –DST_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. 9. If LLI(n) is the last descriptor, then LLI(n).DSCR points to 0 else LLI(n) points to the start address of LLI(n+1). 10. Program DMAC_CTRLBx for the Channel Register x with 0. Its content is updated with the LLI fetch operation. 11.
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–SRC_INCR is set to INCR. –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC). –DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST). –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously. 8. Program the LLI_W(n).
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–SRC_INCR is set to INCR. –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC). –DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST). –DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able to prefetch data and write HSMCI simultaneously. 9. Program the LLI_W(n).
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17. Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If LLI_B(n) is the last descriptor, then program LLI_B(n).DMAC_DSCR with 0. 18. Program the DMAC_CTRLBx register for Channel x with 0, its content is updated with the LLI Fetch operation. 19. Program DMAC_DSCRx with the address of LLI_W(0) if block_length is greater than 4 else with address of LLI_B(0). 20. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request. 4.
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–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. 9. Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then LLI_W(n).DMAC_DSCRx points to 0. 10. Program the DMAC_CTRLBx register for Channel x with 0. its content is updated with the LLI Fetch operation. 11.
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34.9.2 SDIO Interrupts Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO interrupt on each slot can be enabled through the HSMCI Interrupt Enable Register. The SDIO interrupt is sampled regardless of the currently selected slot. 34.
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z Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response. z Issue a software reset to the CE-ATA device using FAST_IO (CMD39). If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if the error recovery procedure does not work as expected or there is another timeout, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets all device states.
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34.12 HSMCI Transfer Done Timings 34.12.1 Definition The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished. 34.12.2 Read Access During a read access, the XFRDONE flag behaves as shown in Figure 34-11. Figure 34-11.XFRDONE During a Read Access CMD line HSMCI read CMD Card response The CMDRDY flag is released 8 tbit after the end of the card response. CMDRDY flag Data Last Block 1st Block Not busy flag XFRDONE flag 34.12.
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34.13 Write Protection Registers To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI address space from address offset 0x000 to 0x00FC can be write-protected by setting the WPEN bit in the “HSMCI Write Protect Mode Register” (HSMCI_WPMR).
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34.14 High Speed MultiMedia Card Interface (HSMCI) User Interface Table 34-8.
PAGE 615
34.14.1 HSMCI Control Register Name: HSMCI_CR Address: 0xF0008000 (0), 0xF000C000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN • MCIEN: Multi-Media Interface Enable 0 = No effect. 1 = Enables the Multi-Media Interface if MCDIS is 0. • MCIDIS: Multi-Media Interface Disable 0 = No effect.
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34.14.2 HSMCI Mode Register Name: HSMCI_MR Address: 0xF0008004 (0), 0xF000C004 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 CLKODD 15 – 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 3 2 1 0 CLKDIV This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.
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34.14.3 HSMCI Data Timeout Register Name: HSMCI_DTOR Address: 0xF0008008 (0), 0xF000C008 (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 DTOMUL 4 3 2 1 0 DTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.
PAGE 618
34.14.4 HSMCI SDCard/SDIO Register Name: HSMCI_SDCR Address: 0xF000800C (0), 0xF000C00C (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 5 – 4 – 3 – 2 – 1 7 SDCBUS 0 SDCSEL This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638. • SDCSEL: SDCard/SDIO Slot Value Name Description 0 SLOTA Slot A is selected.
PAGE 619
34.14.
PAGE 620
34.14.6 HSMCI Command Register Name: HSMCI_CMDR Address: 0xF0008014 (0), 0xF000C014 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 BOOT_ACK 26 ATACS 25 23 – 22 – 21 20 TRTYP 19 18 TRDIR 17 15 – 14 – 13 – 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 6 5 4 3 2 1 0 7 RSPTYP 24 IOSPCMD 16 TRCMD CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD).
PAGE 621
• OPDCMD: Open Drain Command 0 (PUSHPULL) = Push pull command. 1 (OPENDRAIN) = Open drain command. • MAXLAT: Max Latency for Command to Response 0 (5) = 5-cycle max latency. 1 (64) = 64-cycle max latency. • TRCMD: Transfer Command Value Name Description 0 NO_DATA 1 START_DATA Start data transfer 2 STOP_DATA Stop data transfer 3 – No data transfer Reserved • TRDIR: Transfer Direction 0 (WRITE) = Write. 1 (READ) = Read.
PAGE 622
34.14.7 HSMCI Block Register Name: HSMCI_BLKR Address: 0xF0008018 (0), 0xF000C018 (1) Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer.
PAGE 623
34.14.8 HSMCI Completion Signal Timeout Register Name: HSMCI_CSTOR Address: 0xF000801C (0), 0xF000C01C (1) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 CSTOMUL 4 3 2 1 0 CSTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.
PAGE 624
34.14.9 HSMCI Response Register Name: HSMCI_RSPR Address: 0xF0008020 (0), 0xF000C020 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
PAGE 625
34.14.
PAGE 626
34.14.
PAGE 627
34.14.12 HSMCI Status Register Name: HSMCI_SR Address: 0xF0008040 (0), 0xF000C040 (1) Access: Read-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 – 14 – 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 – 6 – 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY • CMDRDY: Command Ready 0 = A command is in progress. 1 = The last command has been sent.
PAGE 628
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block. For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data block. The NOTBUSY flag allows to deal with these different states. 0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response. 1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended.
PAGE 629
• DTOE: Data Time-out Error 0 = No error. 1 = The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the HSMCI_SR register. • CSTOE: Completion Signal Time-out Error 0 = No error. 1 = The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading in the HSMCI_SR register. Cleared by reading in the HSMCI_SR register. • BLKOVRE: DMA Block Overrun Error 0 = No error.
PAGE 630
34.14.
PAGE 631
• FIFOEMPTY: FIFO empty Interrupt enable • XFRDONE: Transfer Done Interrupt enable • ACKRCV: Boot Acknowledge Interrupt Enable • ACKRCVE: Boot Acknowledge Error Interrupt Enable • OVRE: Overrun Interrupt Enable • UNRE: Underrun Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
PAGE 632
34.14.
PAGE 633
• FIFOEMPTY: FIFO empty Interrupt Disable • XFRDONE: Transfer Done Interrupt Disable • ACKRCV: Boot Acknowledge Interrupt Disable • ACKRCVE: Boot Acknowledge Error Interrupt Disable • OVRE: Overrun Interrupt Disable • UNRE: Underrun Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
PAGE 634
34.14.
PAGE 635
• FIFOEMPTY: FIFO Empty Interrupt Mask • XFRDONE: Transfer Done Interrupt Mask • ACKRCV: Boot Operation Acknowledge Received Interrupt Mask • ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask • OVRE: Overrun Interrupt Mask • UNRE: Underrun Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
PAGE 636
34.14.16 HSMCI DMA Configuration Register Name: HSMCI_DMA Address: 0xF0008050 (0), 0xF000C050 (1) Access: Read-write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 ROPT 11 – 10 – 9 – 8 DMAEN 7 – 6 5 CHKSIZE 4 3 – 2 – 1 0 OFFSET This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.
PAGE 637
34.14.17 HSMCI Configuration Register Name: HSMCI_CFG Address: 0xF0008054 (0), 0xF000C054 (1) Access: Read-write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LSYNC 11 – 10 – 9 – 8 HSMODE 7 – 6 – 5 – 4 FERRCTRL 3 – 2 – 1 – 0 FIFOMODE This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.
PAGE 638
34.14.18 HSMCI Write Protect Mode Register Name: HSMCI_WPMR Address: 0xF00080E4 (0), 0xF000C0E4 (1) Access: Read-write 31 30 29 28 27 WP_KEY (0x4D => “M”) 26 25 24 23 22 21 20 19 WP_KEY (0x43 => C”) 18 17 16 15 14 13 12 11 WP_KEY (0x49 => “I”) 10 9 8 7 6 5 2 1 0 WP_EN 4 3 • WP_EN: Write Protection Enable 0 = Disables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII). 1 = Enables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII).
PAGE 639
34.14.
PAGE 640
34.14.20 HSMCI FIFOx Memory Aperture Name: HSMCI_FIFOx[x=0..
PAGE 641
35. Serial Peripheral Interface (SPI) 35.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
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35.3 Block Diagram Figure 35-1. Block Diagram AHB Matrix DMA Ch. Peripheral Bridge APB SPCK MISO PMC MOSI MCK SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 35.4 Application Block Diagram Figure 35-2.
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35.5 Signal Description Table 35-1. Signal Description Pin Name Pin Description Type Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input 35.6 Product Dependencies 35.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
PAGE 644
35.6.3 Interrupt The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires programming the interrupt controller before configuring the SPI. Table 35-3. Peripheral IDs Instance ID SPI0 13 SPI1 14 35.6.4 Direct Memory Access Controller (DMAC) The SPI interface can be used in conjunction with the DMAC in order to reduce processor overhead. For a full description of the DMAC, refer to the corresponding section in the full datasheet. 35.
PAGE 645
Figure 35-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 35-4.
PAGE 646
35.7.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
PAGE 647
35.7.3.1 Master Mode Block Diagram Figure 35-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
PAGE 648
35.7.3.2 Master Mode Flow Diagram Figure 35-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
PAGE 649
Figure 35-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 35-7.
PAGE 650
Figure 35-8. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 35.7.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. z Fixed Peripheral Select: SPI exchanges data with only one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register).
PAGE 651
35.7.3.7 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one NPCS line driven low at a time.
PAGE 652
To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select will remain active.
PAGE 653
35.7.3.10 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO controller).
PAGE 654
Figure 35-11.Slave Mode Functional Bloc Diagram SPCK NSS SPI Clock SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RDRF OVRES RD MSB Shift Register MISO SPI_TDR TD TDRE 35.7.5 Write Protected Registers To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR).
PAGE 655
35.8 Serial Peripheral Interface (SPI) User Interface Table 35-5.
PAGE 656
35.8.1 SPI Control Register Name: SPI_CR Address: 0xF0000000 (0), 0xF0004000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI.
PAGE 657
35.8.2 SPI Mode Register Name: SPI_MR Address: 0xF0000004 (0), 0xF0004004 (1) Access: Read-write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.
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• LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0).
PAGE 659
35.8.3 SPI Receive Data Register Name: SPI_RDR Address: 0xF0000008 (0), 0xF0004008 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
PAGE 660
35.8.4 SPI Transmit Data Register Name: SPI_TDR Address: 0xF000000C (0), 0xF000400C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
PAGE 661
35.8.
PAGE 662
35.8.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0xF0000014 (0), 0xF0004014 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE – – – OVRES MODF TDRE RDRF 0 = No effect. 1 = Enables the corresponding interrupt.
PAGE 663
35.8.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0xF0000018 (0), 0xF0004018 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = No effect. 1 = Disables the corresponding interrupt.
PAGE 664
35.8.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0xF000001C (0), 0xF000401C (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
PAGE 665
35.8.9 SPI Chip Select Register Name: SPI_CSRx[x=0..3] Address: 0xF0000030 (0), 0xF0004030 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT – NCPHA CPOL This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. Note: SPI_CSRx registers must be written even if the user wants to use the defaults.
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Value 8 9 10 11 12 13 14 15 Name 16_BIT – – – – – – – Description 16 bits for transfer Reserved Reserved Reserved Reserved Reserved Reserved Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field.
PAGE 667
35.8.
PAGE 668
35.8.11 SPI Write Protection Status Register Name: SPI_WPSR Address: 0xF00000E8 (0), 0xF00040E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register.
PAGE 669
36. Timer Counter (TC) 36.1 Description The Timer Counter (TC) includes six identical 32-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
PAGE 670
36.
PAGE 671
36.3 Block Diagram Figure 36-1.
PAGE 672
36.4 Pin Name List Table 36-3. TC pin list Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O 36.5 Product Dependencies 36.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 36-4.
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36.6 Functional Description 36.6.1 TC Description The six channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 36-5 on page 685. 36.6.2 32-bit Counter Each channel is organized around a 32-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
PAGE 674
Figure 36-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK0 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 36-3.
PAGE 675
36.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 36-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
PAGE 676
36.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock.
PAGE 677
TIOA TIOB SYNC XC2 XC1 XC0 MTIOA MTIOB 1 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 ABETRG CLKI SWTRG If RA is not loaded or RB is Loaded Edge Detector ETRGEDG MCK Synchronous Edge Detection Edge Detector LDRA S R OVF If RA is Loaded CPCTRG Counter RESET Trig CLK Q LDBSTOP R S CLKEN Edge Detector LDRB Capture Register A Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR Timer/Counter Channel BURST TCCLKS Compare RC = Register C COVFS INT
PAGE 678
36.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
PAGE 679
TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG MCK Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TCCLKS TIOB
PAGE 680
36.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 36-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 36-8. RC Compare cannot be programmed to generate a trigger in this configuration.
PAGE 681
36.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 36-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 36-10.
PAGE 682
36.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 36-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-12.
PAGE 683
36.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 36-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-14.
PAGE 684
36.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
PAGE 685
36.7 Timer Counter (TC) User Interface Table 36-5.
PAGE 686
36.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: 0xF8008000 (0)[0], 0xF8008040 (0)[1], 0xF8008080 (0)[2], 0xF800C000 (1)[0], 0xF800C040 (1)[1], 0xF800C080 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect.
PAGE 687
36.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..
PAGE 688
• LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger.
PAGE 689
36.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..
PAGE 690
• EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event. Value Name Description TIOB Direction 0 TIOB TIOB(1) Input 1 XC0 XC0 Output 2 XC1 XC1 Output 3 XC2 XC2 Output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
PAGE 691
• ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BCPB: RB Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • B
PAGE 692
• BEEVT: External Event Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BSWTRG: Software Trigger Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM9G25 [DATASHEET] 11032C–ATARM–25-Jan-13 692
PAGE 693
36.7.4 TC Counter Value Register Name: TC_CVx [x=0..2] Address: 0xF8008010 (0)[0], 0xF8008050 (0)[1], 0xF8008090 (0)[2], 0xF800C010 (1)[0], 0xF800C050 (1)[1], 0xF800C090 (1)[2] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
PAGE 694
36.7.5 TC Register A Name: TC_RAx [x=0..2] Address: 0xF8008014 (0)[0], 0xF8008054 (0)[1], 0xF8008094 (0)[2], 0xF800C014 (1)[0], 0xF800C054 (1)[1], 0xF800C094 (1)[2] Access: Read-only if WAVE = 0, Read-write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RA 23 22 21 20 RA 15 14 13 12 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real time. 36.7.6 TC Register B Name: TC_RBx [x=0..
PAGE 695
36.7.7 TC Register C Name: TC_RCx [x=0..2] Address: 0xF800801C (0)[0], 0xF800805C (0)[1], 0xF800809C (0)[2], 0xF800C01C (1)[0], 0xF800C05C (1)[1], 0xF800C09C (1)[2] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time.
PAGE 696
36.7.8 TC Status Register Name: TC_SRx [x=0..
PAGE 697
• CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high.
PAGE 698
36.7.9 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Address: 0xF8008024 (0)[0], 0xF8008064 (0)[1], 0xF80080A4 (0)[2], 0xF800C024 (1)[0], 0xF800C064 (1)[1], 0xF800C0A4 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect.
PAGE 699
36.7.10 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Address: 0xF8008028 (0)[0], 0xF8008068 (0)[1], 0xF80080A8 (0)[2], 0xF800C028 (1)[0], 0xF800C068 (1)[1], 0xF800C0A8 (1)[2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect.
PAGE 700
36.7.11 TC Interrupt Mask Register Name: TC_IMRx [x=0..
PAGE 701
36.7.12 TC Block Control Register Name: TC_BCR Address: 0xF80080C0 (0), 0xF800C0C0 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
PAGE 702
36.7.
PAGE 703
37. Two-wire Interface (TWI) 37.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
PAGE 704
37.2 Embedded Characteristics z Three TWIs z Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices(1) z One, Two or Three Bytes for Slave Address z Sequential Read-write Operations z Master, Multi-master and Slave Mode Operation z Bit Rate: Up to 400 Kbits z General Call Supported in Slave mode z SMBUS Quick Command Supported in Master Mode z Connection to DMA Controller (DMA) Channel Capabilities optimizes Data Transfers in Master Mode Only Note: 37.3 1.
PAGE 705
37.4 Block Diagram Figure 37-1. Block Diagram APB Bridge TWCK PIO PMC MCK TWD Two-wire Interface TWI TWI Interrupt Interrupt 37.5 Interrupt AIC Controller Application Block Diagram Figure 37-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 37.5.1 I/O Lines Description Table 37-3.
PAGE 706
37.6 Product Dependencies 37.6.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 37-2 on page 705). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines.
PAGE 707
37.7 Functional Description 37.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 37-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 37-3). z A high-to-low transition on the TWD line while TWCK is high defines the START condition.
PAGE 708
37.8 Master Mode 37.8.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 37.8.2 Application Block Diagram Figure 37-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 37.8.
PAGE 709
Figure 37-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) S TWD DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 37-7.
PAGE 710
Figure 37-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 37.8.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device.
PAGE 711
Figure 37-9. Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 37-10.Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read Figure 37-11.
PAGE 712
37.8.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 37.8.6.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
PAGE 713
37.8.6.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2.
PAGE 714
37.8.8 SMBUS Quick Command (Master Mode Only) The TWI interface can perform a Quick Command: 1. Configure the master mode (DADR, CKDIV, etc.). 2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent. 3. Start the transfer by setting the QUICK bit in the TWI_CR. Figure 37-15.SMBUS Quick Command TWD S DADR R/W A P TXCOMP TXRDY Write QUICK command in TWI_CR 37.8.
PAGE 715
Figure 37-16.
PAGE 716
Figure 37-17.
PAGE 717
Figure 37-18.
PAGE 718
Figure 37-19.
PAGE 719
Figure 37-20.
PAGE 720
Figure 37-21.
PAGE 721
37.9 Multi-master Mode 37.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
PAGE 722
Figure 37-22.Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 37-23.
PAGE 723
Figure 37-24.
PAGE 724
37.10 Slave Mode 37.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 37.10.2 Application Block Diagram Figure 37-25.
PAGE 725
37.10.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 37-27 on page 726. 37.10.4.
PAGE 726
37.10.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
PAGE 727
37.10.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
PAGE 728
Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 37-30 on page 728 describes the clock synchronization in Read mode. Figure 37-30.
PAGE 729
37.10.5.5 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 37-31 on page 729 describes the repeated start + reversal from Read to Write mode. Figure 37-31.
PAGE 730
37.10.6 Read Write Flowcharts The flowchart shown in Figure 37-33 on page 730 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 37-33.
PAGE 731
37.11 Write Protection System In order to bring security to the TWI, a write protection system has been implemented. The write protection mode prevents the write of “TWI Clock Waveform Generator Register” and “TWI Slave Mode Register”. When this mode is enabled and one of the protected registers is written, an error is generated in the “TWI Write Protection Status Register” and the register write request is canceled.
PAGE 732
37.12 Two-wire Interface (TWI) User Interface Table 37-6.
PAGE 733
37.12.1 TWI Control Register Name: TWI_CR Address: 0xF8010000 (0), 0xF8014000 (1), 0xF8018000 (2) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
PAGE 734
• SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0 = No effect. 1 = If Master mode is enabled, a SMBUS Quick Command is sent. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset.
PAGE 735
37.12.
PAGE 736
37.12.3 TWI Slave Mode Register Name: TWI_SMR Address: 0xF8010008 (0), 0xF8014008 (1), 0xF8018008 (2) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the “TWI Write Protection Mode Register”.
PAGE 737
37.12.4 TWI Internal Address Register Name: TWI_IADR Address: 0xF801000C (0), 0xF801400C (1), 0xF801800C (2) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
PAGE 738
37.12.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0xF8010010 (0), 0xF8014010 (1), 0xF8018010 (2) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV This register can only be written if the WPEN bit is cleared in the “TWI Write Protection Mode Register”. TWI_CWGR is only used in Master mode.
PAGE 739
37.12.6 TWI Status Register Name: TWI_SR Address: 0xF8010020 (0), 0xF8014020 (1), 0xF8018020 (2) Access: Read-only Reset: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame.
PAGE 740
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 37-26 on page 725, Figure 37-29 on page 727, Figure 37-31 on page 729 and Figure 37-32 on page 729. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
PAGE 741
• SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 37-29 on page 727 and Figure 37-30 on page 728. • EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0 = A slave access is being performing. 1 = The Slave Access is finished.
PAGE 742
37.12.
PAGE 743
37.12.
PAGE 744
37.12.
PAGE 745
37.12.
PAGE 746
37.12.
PAGE 747
37.12.12 TWI Write Protection Mode Register Name: TWI_WPROT_MODE Address: 0xF80100E4 (0), 0xF80140E4 (1), 0xF80180E4 (2) Access: Read-write 31 30 29 28 27 SECURITY_CODE 26 25 24 23 22 21 20 19 SECURITY_CODE 18 17 16 15 14 13 12 11 SECURITY_CODE 10 9 8 7 – 6 – 5 – 4 – 2 – 1 – 0 WPROT 3 – • SECURITY_CODE: Write protection mode security code This security code is needed to set/reset the WPROT bit value (see Section 37.11 “Write Protection System” for details).
PAGE 748
37.12.13 TWI Write Protection Status Register Name: TWI_WPROT_STATUS Address: 0xF80100E8 (0), 0xF80140E8 (1), 0xF80180E8 (2) Access: Read-only 31 30 29 28 27 WPROTADDR 26 25 24 23 22 21 20 19 WPROTADDR 18 17 16 15 14 13 12 11 WPROTADDR 10 9 8 7 – 6 – 5 – 4 – 2 – 1 – 0 WPROTERR 3 – • WPROTADDR: Write Protection Error Address Indicates the address of the register write request which generated the error. • WPROTERR: Write Protection Error Indicates a write protection error.
PAGE 749
38. Pulse Width Modulation Controller (PWM) 38.1 Description The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
PAGE 750
38.3 Block Diagram Figure 38-1.
PAGE 751
38.4 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 38-1. I/O Line Description 38.5 Name Description Type PWMx PWM Waveform Output for channel x Output Product Dependencies 38.5.1 I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function.
PAGE 752
38.6 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. z Clocked by the system clock, MCK, the clock generator module provides 13 clocks. z Each channel can independently choose one of the clock generator outputs. z Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 38.6.1 PWM Clock Generator Figure 38-2.
PAGE 753
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. 38.6.2 PWM Channel 38.6.2.1 Block Diagram Figure 38-3.
PAGE 754
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (--------------------------------------------------2*X*CPRD*DIVA -) ( 2*X*CPRD*DIVB ) or ---------------------------------------------------MCK MCK z The waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
PAGE 755
Figure 38-5.
PAGE 756
38.6.3 PWM Controller Operations 38.6.3.1 Initialization Before enabling the output channel, this channel must have been configured by the software application: z Configuration of the clock generator if DIVA and DIVB are required z Selection of the clock for each channel (CPRE field in the PWM_CMRx register) z Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) z Configuration of the period for each channel (CPRD in the PWM_CPRDx register).
PAGE 757
Figure 38-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level.
PAGE 758
38.7 Pulse Width Modulation Controller (PWM) User Interface Table 38-4.
PAGE 759
38.7.1 PWM Mode Register Name: PWM_MR Address: 0xF8034000 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 PREB 19 18 10 DIVB 15 – 14 – 13 – 12 – 11 7 6 5 4 3 PREA 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor Value Name Description 0 CLK_OFF CLKA, CLKB clock is turned off 1 CLK_DIV1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 – CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
PAGE 760
38.7.2 PWM Enable Register Name: PWM_ENA Address: 0xF8034004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. 38.7.
PAGE 761
38.7.4 PWM Status Register Name: PWM_SR Address: 0xF803400C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
PAGE 762
38.7.5 PWM Interrupt Enable Register Name: PWM_IER Address: 0xF8034010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x.
PAGE 763
38.7.6 PWM Interrupt Disable Register Name: PWM_IDR Address: 0xF8034014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x.
PAGE 764
38.7.7 PWM Interrupt Mask Register Name: PWM_IMR Address: 0xF8034018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled.
PAGE 765
38.7.8 PWM Interrupt Status Register Name: PWM_ISR Address: 0xF803401C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
PAGE 766
38.7.9 PWM Channel Mode Register Name: PWM_CMR[0..
PAGE 767
38.7.10 PWM Channel Duty Cycle Register Name: PWM_CDTY[0..3] Address: 0xF8034204 [0], 0xF8034224 [1], 0xF8034244 [2], 0xF8034264 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
PAGE 768
38.7.11 PWM Channel Period Register Name: PWM_CPRD[0..3] Address: 0xF8034208 [0], 0xF8034228 [1], 0xF8034248 [2], 0xF8034268 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD Only the first 16 bits (internal channel counter size) are significant.
PAGE 769
38.7.12 PWM Channel Counter Register Name: PWM_CCNT[0..3] Address: 0xF803420C [0], 0xF803422C [1], 0xF803424C [2], 0xF803426C [3] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: • The channel is enabled (writing CHIDx in the PWM_ENA register).
PAGE 770
38.7.13 PWM Channel Update Register Name: PWM_CUPD[0..3] Address: 0xF8034210 [0], 0xF8034230 [1], 0xF8034250 [2], 0xF8034270 [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD CUPD: Channel Update Register This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.
PAGE 771
39. Universal Synchronous Asynchronous Receiver Transmitter (USART) 39.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
PAGE 772
39.2 Embedded Characteristics z Programmable Baud Rate Generator z 5-bit to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications z 1, 1.
PAGE 773
39.3 Block Diagram Figure 39-1. USART Block Diagram (Peripheral) DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS PMC MCK DIV SCK Baud Rate Generator MCK/DIV User Interface SLCK APB Table 39-1.
PAGE 774
39.4 Application Block Diagram Figure 39-2.
PAGE 775
39.5 I/O Lines Description Table 39-2.
PAGE 776
39.6 Product Dependencies 39.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
PAGE 777
39.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. using the USART interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. Table 39-4. Peripheral IDs 39.7 Instance ID USART0 5 USART1 6 USART2 7 USART3 8 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications.
PAGE 778
z z Automatic processing and verification of the “Synch Break” and the “Synch Field” z The “Synch Break” is detected even if it is partially superimposed with a data byte z Automatic Identifier parity calculation/sending and verification z Parity sending and verification can be disabled z Automatic Checksum calculation/sending and verification z Checksum sending and verification can be disabled z Support both “Classic” and “Enhanced” checksum types z Full LIN error checking and reporting z
PAGE 779
39.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
PAGE 780
Table 39-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 39-5. Baud Rate Example (OVER = 0) Source Clock Expected Baud Rate MHz Bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.
PAGE 781
39.7.1.2 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
PAGE 782
39.7.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ------ × f Fi where: z B is the bit rate z Di is the bit-rate adjustment factor z Fi is the clock frequency division factor z f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 39-6. Table 39-6.
PAGE 783
Figure 39-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 39.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR).
PAGE 784
Figure 39-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
PAGE 785
The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character.
PAGE 786
Figure 39-10.Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set.
PAGE 787
effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 39-12 and Figure 39-13 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 39-12.
PAGE 788
In order to increase the compatibility the RXIDLV bit in the US_MAN register allows to inform the USART block of the Rx line idle state value (Rx line undriven), it can be either level one (pull-up) or level zero (pull-down). By default this bit is set to one (Rx line is at level 1 if undriven). Figure 39-14.
PAGE 789
When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register.
PAGE 790
Figure 39-18.ASK Modulator Output 1 0 0 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 Figure 39-19.FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 39.7.3.6 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock.
PAGE 791
39.7.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1. Figure 39-21.
PAGE 792
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1. Figure 39-22 illustrates the parity bit status setting and clearing. Figure 39-22.Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 39.7.3.
PAGE 793
Figure 39-23.Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 39-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 39-10. Maximum Timeguard Length Depending on Baud Rate Baud Rate Bit time Timeguard Bit/sec µs ms 1 200 833 212.50 9 600 104 26.
PAGE 794
This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected.
PAGE 795
39.7.3.12 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1.
PAGE 796
Figure 39-26.Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 STTBRK = 1 D6 D7 Parity Stop Bit Bit Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 39.7.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR.
PAGE 797
39.7.3.15 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 39-27. Figure 39-27.Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2.
PAGE 798
Figure 39-29.Connection of a Smart Card to the USART USART CLK SCK Smart Card I/O TXD When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode.
PAGE 799
Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is to 1, no error signal is driven on the I/O line even if a parity bit is detected.
PAGE 800
Figure 39-32.Connection to IrDA Transceivers USART IrDA Transceivers Receiver Demodulator RXD Transmitter Modulator TXD RX TX The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: z Disable TX and Enable RX z Configure the TXD pin as PIO and set it as an output to 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption).
PAGE 801
39.7.5.2 IrDA Baud Rate Table 39-13 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 39-13. IrDA Baud Rate Error Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.
PAGE 802
Figure 39-34.IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input 5 4 3 Pulse Rejected 2 6 6 5 4 3 2 1 0 Pulse Accepted As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 39.7.6 RS485 Mode The USART features the RS485 mode to enable line driver control.
PAGE 803
Figure 39-36.Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 39.7.7 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.
PAGE 804
Operation in SPI Slave Mode is programmed by writing to 0xF the USART_MODE field in the Mode Register.
PAGE 805
39.7.7.3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode (Master or Slave).
PAGE 806
Figure 39-38.SPI Transfer Format (CPHA=0, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 5 8 7 6 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 39.7.7.4 Receiver and Transmitter Control See “Receiver and Transmitter Control” on page 783. 39.7.7.
PAGE 807
39.7.7.6 Character Reception When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
PAGE 808
39.7.8.6 Header Transmission (Master Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. So in Master node configuration, the frame handling starts with the sending of the header. The header is transmitted as soon as the identifier is written in the LIN Identifier register (US_LINIR). At this moment the flag TXRDY falls.
PAGE 809
The flags LINID and LINBK are reset by writing the bit RSTSTA to 1 in the Control register (US_CR). Figure 39-40.Header Reception Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit LINBK LINID US_LINIR Write RSTSTA=1 in US_CR 39.7.8.8 Slave Node Synchronization The synchronization is done only in Slave node configuration.
PAGE 810
Figure 39-42.
PAGE 811
39.7.8.9 Identifier Parity A protected identifier consists of two sub-fields; the identifier and the identifier parity. Bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. The USART interface can generate/check these parity bits, but this feature can also be disabled.
PAGE 812
39.7.8.11 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1).
PAGE 813
39.7.8.13 Frame Slot Mode This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to TFrame_Maximum. If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to TFrame_Maximum.
PAGE 814
Inconsistent Synch Field Error This error is generated in Slave node configuration, if the Synch Field character received is other than 0x55. This error is reported by flag LINISFE in the Channel Status Register (US_CSR). Identifier Parity Error This error is generated in Slave node configuration, if the parity of the identifier is wrong. This error can be generated only if the parity feature is enabled (PARDIS = 0). This error is reported by flag LINIPE in the Channel Status Register (US_CSR).
PAGE 815
Figure 39-45.Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Checksum Data N TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 39-46.
PAGE 816
Figure 39-47.Master Node Configuration, NACT=IGNORE Frame slot = TFrame_Maximum Frame Break Response space Header Data3 Synch Protected Identifier Interframe space Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR LINTC Slave Node Configuration z Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver. z Write USART_MODE in US_MR to select the LIN mode and the Slave Node configuration.
PAGE 817
Figure 39-48.Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 39-49.Slave Node Configuration, NACT = SUBSCRIBE Break Synch Protected Identifier Data 1 Data N-1 TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 39-50.
PAGE 818
Master Node Configuration The user can choose between two DMAC modes by the PDCM bit in the LIN Mode register (US_LINMR): z PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the DMAC in the Transmit Holding register US_THR (instead of the LIN Mode register US_LINMR). Because the DMAC transfer size is limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS are written.
PAGE 819
Slave Node Configuration In this configuration, the DMAC transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (US_LINIR). The LIN mode must be written by the user in the LIN Mode register (US_LINMR). The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT=SUBSCRIBE). Figure 39-53.
PAGE 820
If RETTO is performed, the counter starts counting down immediately from the value TO. Table 39-16. Receiver Time-out programming LIN Specification 2.0 1.3 Baud Rate Time-out period TO 1 000 bit/s 4 000 2 400 bit/s 9 600 9 600 bit/s 4s 38 400 19 200 bit/s 76 800 20 000 bit/s 80 000 - 25 000 Tbits 25 000 39.7.9 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows onboard diagnostics.
PAGE 821
Figure 39-56.Local Loopback Mode Configuration RXD Receiver 1 Transmitter TXD 39.7.9.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 39-57. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 39-57.
PAGE 822
39.7.10 Write Protection Registers To prevent any single software error that may corrupt USART behavior, certain address spaces can be write-protected by setting the WPEN bit in the USART Write Protect Mode Register (US_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register (US_WPSR) is set and the WPVSRC field indicates in which register the write access has been attempted.
PAGE 823
39.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 39-17.
PAGE 824
39.8.1 USART Control Register Name: US_CR Address: 0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS 18 RTSEN 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, see “USART Control Register (SPI_MODE)” on page 826. • RSTRX: Reset Receiver 0: No effect.
PAGE 825
• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
PAGE 826
39.8.2 USART Control Register (SPI_MODE) Name: US_CR (SPI_MODE) Address: 0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 828. • RSTRX: Reset Receiver 0: No effect.
PAGE 827
• FCS: Force SPI Chip Select – Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): FCS = 0: No effect. FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer). • RCS: Release SPI Chip Select – Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin).
PAGE 828
39.8.3 USART Mode Register Name: US_MR Address: 0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3) Access: Read-write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 – 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 15 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 861.
PAGE 829
• CHRL: Character Length. Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode.
PAGE 830
• CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
PAGE 831
39.8.4 USART Mode Register (SPI_MODE) Name: US_MR (SPI_MODE) Address: 0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 18 – 17 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 7 6 5 4 3 2 1 0 CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 828.
PAGE 832
• CHMODE: Channel Mode Value Name Description 0 NORMAL Normal Mode 1 AUTOMATIC 2 LOCAL_LOOPBACK 3 REMOTE_LOOPBACK Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • CPOL: SPI Clock Polarity – Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF): CPOL = 0: The inactive state value of SPCK is logic level zero.
PAGE 833
39.8.5 USART Interrupt Enable Register Name: US_IER Address: 0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)” on page 834.
PAGE 834
39.8.6 USART Interrupt Enable Register (SPI_MODE) Name: US_IER (SPI_MODE) Address: 0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 828.
PAGE 835
39.8.
PAGE 836
39.8.8 USART Interrupt Disable Register Name: US_IDR Address: 0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” on page 837.
PAGE 837
39.8.9 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Address: 0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 828.
PAGE 838
39.8.
PAGE 839
39.8.11 USART Interrupt Mask Register Name: US_IMR Address: 0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Mask Register (SPI_MODE)” on page 840.
PAGE 840
39.8.12 USART Interrupt Mask Register (SPI_MODE) Name: US_IMR (SPI_MODE) Address: 0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 828.
PAGE 841
39.8.
PAGE 842
39.8.14 USART Channel Status Register Name: US_CSR Address: 0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)” on page 844.
PAGE 843
• TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • ITER: MaxNumber of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. • NACK: Non Acknowledge Interrupt 0: Non Acknowledge has not been detected since the last RSTNACK.
PAGE 844
39.8.15 USART Channel Status Register (SPI_MODE) Name: US_CSR (SPI_MODE) Address: 0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 828.
PAGE 845
39.8.
PAGE 846
• LINBK: LIN Break Sent or LIN Break Received – Applicable if USART operates in LIN Master Mode (USART_MODE = 0xA): 0: No LIN Break has been sent since the last RSTSTA. 1:At least one LIN Break has been sent since the last RSTSTA – If USART operates in LIN Slave Mode (USART_MODE = 0xB): 0: No LIN Break has received sent since the last RSTSTA. 1:At least one LIN Break has been received since the last RSTSTA.
PAGE 847
39.8.17 USART Receive Holding Register Name: US_RHR Address: 0xF801C018 (0), 0xF8020018 (1), 0xF8024018 (2), 0xF8028018 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
PAGE 848
39.8.18 USART Transmit Holding Register Name: US_THR Address: 0xF801C01C (0), 0xF802001C (1), 0xF802401C (2), 0xF802801C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
PAGE 849
39.8.19 USART Baud Rate Generator Register Name: US_BRGR Address: 0xF801C020 (0), 0xF8020020 (1), 0xF8024020 (2), 0xF8028020 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 861.
PAGE 850
39.8.20 USART Receiver Time-out Register Name: US_RTOR Address: 0xF801C024 (0), 0xF8020024 (1), 0xF8024024 (2), 0xF8028024 (3) Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 861. • TO: Time-out Value 0: The Receiver Time-out is disabled.
PAGE 851
39.8.21 USART Transmitter Timeguard Register Name: US_TTGR Address: 0xF801C028 (0), 0xF8020028 (1), 0xF8024028 (2), 0xF8028028 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 861. • TG: Timeguard Value 0: The Transmitter Timeguard is disabled.
PAGE 852
39.8.22 USART FI DI RATIO Register Name: US_FIDI Address: 0xF801C040 (0), 0xF8020040 (1), 0xF8024040 (2), 0xF8028040 (3) Access: Read-write Reset Value: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 861.
PAGE 853
39.8.23 USART Number of Errors Register Name: US_NER Address: 0xF801C044 (0), 0xF8020044 (1), 0xF8024044 (2), 0xF8028044 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE=0x4 or 0x6 in “USART Mode Register” on page 828.
PAGE 854
39.8.24 USART IrDA FILTER Register Name: US_IF Address: 0xF801C04C (0), 0xF802004C (1), 0xF802404C (2), 0xF802804C (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register is relevant only if USART_MODE=0x8 in “USART Mode Register” on page 828.
PAGE 855
39.8.25 USART Manchester Configuration Register Name: US_MAN Address: 0xF801C050 (0), 0xF8020050 (1), 0xF8024050 (2), 0xF8028050 (3) Access: Read-write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 17 16 RX_PL 8 TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 861.
PAGE 856
01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s • RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the US_MAN register.
PAGE 857
39.8.26 USART LIN Mode Register Name: US_LINMR Address: 0xF801C054 (0), 0xF8020054 (1), 0xF8024054 (2), 0xF8028054 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 0 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP NACT This register is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 828.
PAGE 858
• FSDIS: Frame Slot Mode Disable 0: The Frame Slot Mode is enabled. 1: The Frame Slot Mode is disabled. • WKUPTYP: Wakeup Signal Type 0: Setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal. 1: Setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. • DLC: Data Length Control 0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes.
PAGE 859
39.8.27 USART LIN Identifier Register Name: US_LINIR Address: 0xF801C058 (0), 0xF8020058 (1), 0xF8024058 (2), 0xF8028058 (3) Access: Read-write or Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR This register is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 828.
PAGE 860
39.8.28 USART LIN Baud Rate Register Name: US_LINBRR Address: 0xF801C05C (0), 0xF802005C (1), 0xF802405C (2), 0xF802805C (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 LINFP 16 15 14 13 12 11 10 9 8 3 2 1 0 LINCD 7 6 5 4 LINCD This register is relevant only if USART_MODE=0xA or 0xB in “USART Mode Register” on page 828. Returns the baud rate value after the synchronization process completion.
PAGE 861
39.8.29 USART Write Protect Mode Register Name: US_WPMR Address: 0xF801C0E4 (0), 0xF80200E4 (1), 0xF80240E4 (2), 0xF80280E4 (3) Access: Read-write Reset: See Table 39-17 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
PAGE 862
39.8.30 USART Write Protect Status Register Name: US_WPSR Address: 0xF801C0E8 (0), 0xF80200E8 (1), 0xF80240E8 (2), 0xF80280E8 (3) Access: Read-only Reset: See Table 39-17 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the US_WPSR register.
PAGE 863
40. Analog-to-Digital Converter (ADC) 40.1 Description The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the Block Diagram: Figure 40-1. It also integrates a 12-to-1 analog multiplexer, making possible the analog-to-digital conversions of 12 analog lines. The conversions extend from 0V to ADVREF.
PAGE 864
40.
PAGE 865
40.3 Block Diagram Figure 40-1. Analog-to-Digital Converter Block Diagram Timer Counter Channels PMC MCK ADC Controller Trigger Selection ADTRG Control Logic ADC Interrupt Interrupt Controller ADC cell ADVREF System Bus PDC User Interface AD- Analog Inputs Multiplexed with I/O lines PIO Peripheral Bridge Successive Approximation Register Analog-to-Digital Converter APB ADCHx AD- GND Note: 40.4 DMA is sometimes referenced as PDC (Peripheral DMA Controller).
PAGE 866
40.5 Product Dependencies 40.5.1 Power Management The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the Power Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled. 40.5.
PAGE 867
40.6 Functional Description 40.6.1 Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data requires Tracking Clock cycles as defined in the field TRACKTIM of the “ADC Mode Register” on page 874 and Transfer Clock cycles as defined in the field TRANSFER of the same register. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR).
PAGE 868
40.6.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDRx) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). By setting the TAG option in the ADC_EMR, the ADC_LCDR presents the channel number associated to the last converted data in the CHNB field. The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set.
PAGE 869
Figure 40-4.
PAGE 870
Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers permit the analog channels to be enabled or disabled independently.
PAGE 871
The flag can be read on the COMPE bit of the Interrupt Status Register (ADC_ISR) and can trigger an interrupt. The High Threshold and the Low Threshold can be read/write in the Comparison Window Register (ADC_CWR). If the comparison window is to be used with LOWRES bit in ADC_MR set to 1, the thresholds do not need to be adjusted as adjustment will be done internally. Whether or not the LOWRES bit is set, thresholds must always be configured in consideration of the maximum ADC resolution. 40.6.
PAGE 872
40.7 Analog-to-Digital Converter (ADC) User Interface Any offset not listed in Table 40-4 must be considered as “reserved”. Table 40-4.
PAGE 873
40.7.1 ADC Control Register Name: ADC_CR Address: 0xF804C000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 START 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion.
PAGE 874
40.7.2 ADC Mode Register Name: ADC_MR Address: 0xF804C004 Access: Read-write 31 USEQ 30 – 29 – 28 – 27 23 – 22 – 21 – 20 – 19 15 14 13 12 26 25 24 17 16 TRACKTIM 18 STARTUP 11 10 9 8 PRESCAL 7 6 5 4 3 2 1 0 – FWUP SLEEP LOWRES – – – – This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 891.
PAGE 875
Value Name Description 5 SUT80 80 periods of ADCClock 6 SUT96 96 periods of ADCClock 7 SUT112 112 periods of ADCClock 8 SUT512 512 periods of ADCClock 9 SUT576 576 periods of ADCClock 10 SUT640 640 periods of ADCClock 11 SUT704 704 periods of ADCClock 12 SUT768 768 periods of ADCClock 13 SUT832 832 periods of ADCClock 14 SUT896 896 periods of ADCClock 15 SUT960 960 periods of ADCClock • TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) * ADCClock periods.
PAGE 876
40.7.3 ADC Channel Sequence 1 Register Name: ADC_SEQR1 Address: 0xF804C008 Access: Read-write 31 30 29 28 27 26 USCH8 23 22 21 20 19 18 USCH6 15 14 13 6 24 17 16 9 8 1 0 USCH5 12 11 10 USCH4 7 25 USCH7 USCH3 5 4 USCH2 3 2 USCH1 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 891.
PAGE 877
40.7.4 ADC Channel Sequence 2 Register Name: ADC_SEQR2 Address: 0xF804C00C Access: Read-write 31 30 29 28 27 26 USCH16 23 22 21 20 19 18 USCH14 15 14 13 6 24 17 16 9 8 1 0 USCH13 12 11 10 USCH12 7 25 USCH15 USCH11 5 4 USCH10 3 2 USCH9 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 891.
PAGE 878
40.7.5 ADC Channel Enable Register Name: ADC_CHER Address: 0xF804C010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 891. • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel.
PAGE 879
40.7.6 ADC Channel Disable Register Name: ADC_CHDR Address: 0xF804C014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 891. • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel.
PAGE 880
40.7.7 ADC Channel Status Register Name: ADC_CHSR Address: 0xF804C018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
PAGE 881
40.7.8 ADC Last Converted Data Register Name: ADC_LCDR Address: 0xF804C020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 0 CHNB 7 6 LDATA 5 4 3 2 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
PAGE 882
40.7.9 ADC Interrupt Enable Register Name: ADC_IER Address: 0xF804C024 Access: Write-only 31 – 30 29 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 21 20 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion Interrupt Enable x • DRDY: Data Ready Interrupt Enable • GOVRE: General Overrun Error Interrupt Enable • COMPE: Comparison Event Interrupt Enable 0 = No effect.
PAGE 883
40.7.10 ADC Interrupt Disable Register Name: ADC_IDR Address: 0xF804C028 Access: Write-only 31 – 30 29 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 21 20 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion Interrupt Disable x • DRDY: Data Ready Interrupt Disable • GOVRE: General Overrun Error Interrupt Disable • COMPE: Comparison Event Interrupt Disable 0 = No effect.
PAGE 884
40.7.11 ADC Interrupt Mask Register Name: ADC_IMR Address: 0xF804C02C Access: Read-only 31 – 30 29 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 21 20 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion Interrupt Mask x • DRDY: Data Ready Interrupt Mask • GOVRE: General Overrun Error Interrupt Mask • COMPE: Comparison Event Interrupt Mask 0 = No effect.
PAGE 885
40.7.12 ADC Interrupt Status Register Name: ADC_ISR Address: 0xF804C030 Access: Read-only 31 30 29 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 21 20 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the corresponding ADC_CDRx registers.
PAGE 886
40.7.13 ADC Overrun Status Register Name: ADC_OVER Address: 0xF804C03C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 • OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_OVER.
PAGE 887
40.7.14 ADC Extended Mode Register Name: ADC_EMR Address: 0xF804C040 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 TAG 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 – 10 – 9 CMPALL 8 – 7 6 4 3 – 2 – 1 0 CMPFILTER 5 CMPSEL CMPMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 891.
PAGE 888
40.7.15 ADC Compare Window Register Name: ADC_CWR Address: 0xF804C044 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 HIGHTHRES 19 18 11 10 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 891. • LOWTHRES: Low Threshold Low threshold associated to compare settings of the ADC_EMR register.
PAGE 889
40.7.16 ADC Channel Data Register Name: ADC_CDRx [x=0..11] Address: 0xF804C050 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
PAGE 890
40.7.
PAGE 891
40.7.18 ADC Write Protect Mode Register Name: ADC_WPMR Address: 0xF804C0E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
PAGE 892
40.7.19 ADC Write Protect Status Register Name: ADC_WPSR Address: 0xF804C0E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the ADC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the ADC_WPSR register.
PAGE 893
41. Universal Asynchronous Receiver Transmitter (UART) 41.1 Description The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with DMA controller permits packet handling for these tasks with processor time reduced to a minimum. 41.
PAGE 894
41.3 Block Diagram Figure 41-1. UART Functional Block Diagram Peripheral Bridge DMA Controller APB UART UTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive URXD Interrupt Control uart_irq Table 41-1.
PAGE 895
41.4 Product Dependencies 41.4.1 I/O Lines The UART pins are multiplexed with PIO lines. The programmer must first configure the corresponding PIO Controller to enable I/O line operations of the UART. Table 41-2. I/O Lines Instance Signal I/O Line Peripheral UART0 URXD0 PC9 C UART0 UTXD0 PC8 C UART1 URXD1 PC17 C UART1 UTXD1 PC16 C 41.4.2 Power Management The UART clock is controllable through the Power Management Controller.
PAGE 896
Figure 41-2. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 41.5.2 Receiver 41.5.2.1 Receiver Reset, Enable and Disable After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register UART_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
PAGE 897
Figure 41-4. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period URXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 41.5.2.3 Receiver Ready When a complete character is received, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is read. Figure 41-5.
PAGE 898
Figure 41-7. Parity Error URXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA 41.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit RSTSTA at 1. Figure 41-8.
PAGE 899
Figure 41-9. Character Transmission Example: Parity enabled Baud Rate Clock UTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 41.5.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register UART_SR. The transmission starts when the programmer writes in the Transmit Holding Register (UART_THR), and after the written character is transferred from UART_THR to the Shift Register.
PAGE 900
Figure 41-11.
PAGE 901
41.6 Universal Asynchronous Receiver Transmitter (UART) User Interface Table 41-3.
PAGE 902
41.6.1 UART Control Register Name: UART_CR Address: 0xF8040000 (0), 0xF8044000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
PAGE 903
41.6.
PAGE 904
41.6.
PAGE 905
41.6.
PAGE 906
41.6.
PAGE 907
41.6.6 UART Status Register Name: UART_SR Address: 0xF8040014 (0), 0xF8044014 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the UART_RHR or the receiver is disabled.
PAGE 908
41.6.7 UART Receiver Holding Register Name: UART_RHR Address: 0xF8040018 (0), 0xF8044018 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
PAGE 909
41.6.8 UART Transmit Holding Register Name: UART_THR Address: 0xF804001C (0), 0xF804401C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
PAGE 910
41.6.
PAGE 911
42. Software Modem Device (SMD) 42.1 Description The Software Modem Device (SMD) is a block for communication via a modem's Digital Isolation Barrier (DIB) with a complementary Line Side Device (HLSD). SMD and HLSD are two parts of the "Transformer only" solution. The transformer is the only component connecting SMD and HLSD. The transformer is used for power, clock and data transfers. Power and clock are supplied by the SMD and consumed by the HLSD. The data flow is bidirectional.
PAGE 912
42.3 Block Diagram Figure 42-1.
PAGE 913
43. Synchronous Serial Controller (SSC) 43.1 Description The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
PAGE 914
43.3 Block Diagram Figure 43-1. Block Diagram System Bus APB Bridge DMA Peripheral Bus TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 43.4 Application Block Diagram Figure 43-2.
PAGE 915
43.5 Pin Name List Table 43-1. I/O Lines Description Pin Name Pin Description RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 43.6 Type Product Dependencies 43.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
PAGE 916
43.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
PAGE 917
43.7.1 Clock Management The transmitter clock can be generated by: z an external clock received on the TK I/O pad z the receiver clock z the internal clock divider The receiver clock can be generated by: z an external clock received on the RK I/O pad z the transmitter clock z the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.
PAGE 918
43.7.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register.
PAGE 919
Figure 43-7. Receiver Clock Management RK (pin) Tri-state Controller MUX Clock Output Transmitter Clock Divider Clock Data Transfer CKO CKS INV MUX Tri-state Controller CKI CKG Receiver Clock 43.7.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers.
PAGE 920
Figure 43-8. Transmitter Block Diagram SSC_CRTXEN TXEN SSC_SRTXEN SSC_CRTXDIS SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_RCMR.START SSC_TCMR.START SSC_TFMR.DATNB SSC_TFMR.DATDEF SSC_TFMR.MSBF RXEN TXEN TX Start TX Start Start RX Start Start RF Selector Selector RF RC0R TX Controller TD Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY != 0 SSC_TFMR.DATLEN 0 SSC_THR Transmitter Clock 1 SSC_TSHR SSC_TFMR.FSLEN TX Controller counter reached STTDLY 43.7.
PAGE 921
Figure 43-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS SSC_TCMR.START SSC_RCMR.START TXEN RX Start RF Start Selector RXEN RF RC0R SSC_RFMR.MSBF SSC_RFMR.DATNB RX Start Start Selector RX Controller RD Receive Shift Register SSC_RCMR.STTDLY != 0 load SSC_RSHR load SSC_RFMR.FSLEN SSC_RHR Receiver Clock SSC_RFMR.DATLEN RX Controller counter reached STTDLY 43.7.
PAGE 922
Figure 43-10.Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF TD (Output) TD (Output) X BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) TD (Output) B1 STTDLY BO X B1 STTDLY TD Start = Level Change on TF (Output) Start = Any Edge on TF BO BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 43-11.
PAGE 923
43.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. z Programmable low or high levels during data transfer are supported. z Programmable high levels before the start of data transfers or toggling are also supported.
PAGE 924
43.7.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: z the event that starts the data transfer (START) z the delay in number of bit periods between the start event and the first data bit (STTDLY) z the length of the data (DATLEN) z the number of data to be transferred for each start event (DATNB).
PAGE 925
Figure 43-14.Transmit Frame Format in Continuous Mode Start Data TD Default Data From SSC_THR From SSC_THR DATLEN DATLEN Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 43-15.Receive Frame Format in Continuous Mode Start = Enable Receiver RD Note: 1.
PAGE 926
Figure 43-16.
PAGE 927
43.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 43-17.Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB MSB Right Channel Left Channel Figure 43-18.
PAGE 928
Figure 43-19.
PAGE 929
43.8.1 Write Protection Registers To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
PAGE 930
43.9 Synchronous Serial Controller (SSC) User Interface Table 43-5.
PAGE 931
43.9.1 SSC Control Register Name: SSC_CR: Address: 0xF0010000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive.
PAGE 932
43.9.2 SSC Clock Mode Register Name: SSC_CMR Address: 0xF0010004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV.
PAGE 933
43.9.3 SSC Receive Clock Mode Register Name: SSC_RCMR Address: 0xF0010010 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 STOP 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
PAGE 934
• CKG: Receive Clock Gating Selection Value Name Description 0 CONTINUOUS None 1 EN_RF_LOW Receive Clock enabled only if RF Pin is Low 2 EN_RF_HIGH Receive Clock enabled only if RF Pin is High • START: Receive Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
PAGE 935
43.9.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0xF0010014 Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 – 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
PAGE 936
Value Name Description 3 LOW Driven Low during data transfer, RF pin is an output 4 HIGH Driven High during data transfer, RF pin is an output 5 TOGGLING Toggling at each start of data transfer, RF pin is an output • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
PAGE 937
43.9.5 SSC Transmit Clock Mode Register Name: SSC_TCMR Address: 0xF0010018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 – 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
PAGE 938
• START: Transmit Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
PAGE 939
43.9.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0xF001001C Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 FSDEN 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
PAGE 940
Value Name Description 3 LOW TF pin Driven Low during data transfer 4 HIGH TF pin Driven High during data transfer 5 TOGGLING TF pin Toggles at each start of data transfer • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal. 1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
PAGE 941
43.9.7 SSC Receive Holding Register Name: SSC_RHR Address: 0xF0010020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 43.9.
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43.9.9 SSC Receive Synchronization Holding Register Name: SSC_RSHR Address: 0xF0010030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT • RSDAT: Receive Synchronization Data 43.9.
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43.9.11 SSC Receive Compare 0 Register Name: SSC_RC0R Address: 0xF0010038 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • CP0: Receive Compare Data 0 43.9.
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43.9.13 SSC Status Register Name: SSC_SR Address: 0xF0010040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.
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• TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled. • RXEN: Receive Enable 0 = Receive is disabled. 1 = Receive is enabled.
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43.9.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0xF0010044 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt.
PAGE 947
43.9.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0xF0010048 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt.
PAGE 948
43.9.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0xF001004C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.
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43.9.17 SSC Write Protect Mode Register Name: SSC_WPMR Address: 0xF00100E4 Access: Read-write Reset: See Table 43-5 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
PAGE 950
43.9.18 SSC Write Protect Status Register Name: SSC_WPSR Address: 0xF00100E8 Access: Read-only Reset: See Table 43-5 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register.
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44. Image Sensor Interface (ISI) 44.1 Description The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller.
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44.2 Embedded Characteristics z Compatible with an Embedded 32-bit Microcontroller z ITU-R BT. 601/656 8-bit Mode External Interface Support z Supports up to 12-bit Grayscale CMOS Sensors z Support for ITU-R BT.
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44.
PAGE 954
44.4 Functional Description The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock.
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Figure 44-3. HSYNC and VSYNC Synchronization Frame ISI_VSYNC 1 line ISI_HSYNC ISI_PCK DATA[7..0] Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Figure 44-4. SAV and EAV Sequence Synchronization ISII_PCK DATA[7..0] FF 00 00 SAV 80 Y Cb Y Cr Y Cb Y Cr Active Video Y Y Cr Y Cb FF 00 00 EAV 9D 44.4.2 Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding.
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Table 44-4. RGB Format, RGB_CFG = 10 (Mode 2), No Swap Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 0 G2(i) G1(i) G0(i) R4(i) R3(i) R2(i) R1(i) R0(i) Byte 1 B4(i) B3(i) B2(i) B1(i) B0(i) G5(i) G4(i) G3(i) Byte 2 G2(i+1) G1(i+1) G0(i+1) R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) Byte 3 B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) G5(i+1) G4(i+1) G3(i+1) RGB 5:6:5 Table 44-5.
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44.4.4 Preview Path 44.4.4.1 Scaling, Decimation (Subsampling) This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. Table 44-6. Decimation Factor Dec value 0->15 16 17 18 19 ... 124 125 126 127 Dec Factor X 1 1.063 1.
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Figure 44-5. Resize Examples 1280 32/16 decimation 640 1024 480 1280 56/16 decimation 352 1024 288 44.4.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: Y – Y off C0 0 C1 R G = C 0 – C 2 – C 3 × C b – C boff B C0 C4 0 C r – C roff Example of programmable value to convert YCrCb to RGB: R = 1.
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44.4.4.3 Memory Interface Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:6:5 format compliant with 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue channels, and two LSBs from the green channel.
PAGE 960
Figure 44-6. Three Frame Buffers Application and Memory Mapping Codec Done Codec Request frame n-1 frame n frame n+1 frame n+2 frame n+3 frame n+4 Memory Space Frame Buffer 3 Frame Buffer 0 LCD Frame Buffer 1 ISI config Space 4:2:2 Image Full ROI 44.4.5 Codec Path 44.4.5.1 Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module.
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44.5 Image Sensor Interface (ISI) User Interface Table 44-9.
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44.5.1 ISI Configuration 1 Register Name: ISI_CFG1 Address: 0xF8048000 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 SFD 23 22 21 20 SLD 15 – 14 7 CRC_SYNC 6 EMB_SYNC 13 12 FULL 11 DISCR 10 9 FRATE 8 5 – 4 PIXCLK_POL 3 VSYNC_POL 2 HSYNC_POL 1 – 0 – THMASK • HSYNC_POL: Horizontal Synchronization Polarity 0: HSYNC active high. 1: HSYNC active low. • VSYNC_POL: Vertical Synchronization Polarity 0: VSYNC active high. 1: VSYNC active low.
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• THMASK: Threshold Mask Value Name Description 0 BEATS_4 Only 4 beats AHB burst allowed 1 BEATS_8 Only 4 and 8 beats AHB burst allowed 2 BEATS_16 4, 8 and 16 beats AHB burst allowed • SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. • SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame.
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44.5.2 ISI Configuration 2 Register Name: ISI_CFG2 Address: 0xF8048004 Access: Read-write Reset: 0x00000000 31 30 29 RGB_CFG 23 28 YCC_SWAP 22 21 20 27 - 26 25 IM_HSIZE 24 19 18 17 16 IM_HSIZE 15 COL_SPACE 14 RGB_SWAP 13 GRAYSCALE 12 RGB_MODE 11 GS_MODE 10 9 IM_VSIZE 8 7 6 5 4 3 2 1 0 IM_VSIZE • IM_VSIZE: Vertical Size of the Image Sensor [0..2047]: Vertical size = IM_VSIZE + 1. • GS_MODE: 0: 2 pixels per word. 1: 1 pixel per word.
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• YCC_SWAP: Defines the YCC Image Data YCC_SWAP Byte 0 Byte 1 Byte 2 Byte 3 00: Default Cb(i) Y(i) Cr(i) Y(i+1) 01: Mode1 Cr(i) Y(i) Cb(i) Y(i+1) 10: Mode2 Y(i) Cb(i) Y(i+1) Cr(i) 11: Mode3 Y(i) Cr(i) Y(i+1) Cb(i) • RGB_CFG: Defines RGB Pattern when RGB_MODE is set to 1 RGB_CFG Byte 0 Byte 1 Byte 2 Byte 3 00: Default R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B 01: Mode1 B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R 10: Mode2 G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB) 11: Mode3 G(LSB)/B
PAGE 966
44.5.3 ISI Preview Register Name: ISI_PSIZE Address: 0xF8048008 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 19 18 17 11 – 10 – 9 3 2 1 24 PREV_HSIZE 16 PREV_HSIZE 15 – 14 – 13 – 12 – 7 6 5 4 8 PREV_VSIZE 0 PREV_VSIZE • PREV_VSIZE: Vertical Size for the Preview Path Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode).
PAGE 967
44.5.4 ISI Preview Decimation Factor Register Name: ISI_PDECF Address: 0xF804800C Access: Read-write Reset: 0x00000010 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 DEC_FACTOR • DEC_FACTOR: Decimation Factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation.
PAGE 968
44.5.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register Name: ISI_Y2R_SET0 Address: 0xF8048010 Access: Read-write Reset: 0x6832cc95 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 C3 23 22 21 20 C2 15 14 13 12 C1 7 6 5 4 C0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/128, ranges from 0 to 1.9921875. • C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, ranges from 0 to 1.9921875.
PAGE 969
44.5.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register Name: ISI_Y2R_SET1 Address: 0xF8048014 Access: Read-write Reset: 0x00007102 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 Cboff 13 Croff 12 Yoff 11 – 10 – 9 – 8 C4 7 6 5 4 3 2 1 0 C4 • C4: Color Space Conversion Matrix Coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875. • Yoff: Color Space Conversion Luminance Default Offset 0: No offset.
PAGE 970
44.5.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register Name: ISI_R2Y_SET0 Address: 0xF8048018 Access: Read-write Reset: 0x01324145 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Roff 23 – 22 21 20 19 C2 18 17 16 15 – 14 13 12 11 C1 10 9 8 7 – 6 5 4 3 C0 2 1 0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375. • C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875.
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44.5.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register Name: ISI_R2Y_SET1 Address: 0xF804801C Access: Read-write Reset: 0x01245e38 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Goff 23 – 22 21 20 19 C5 18 17 16 15 – 14 13 12 11 C4 10 9 8 7 – 6 5 4 3 C3 2 1 0 • C3: Color Space Conversion Matrix Coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875.
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44.5.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register Name: ISI_R2Y_SET2 Address: 0xF8048020 Access: Read-write Reset: 0x01384a4b 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Boff 23 – 22 21 20 19 C8 18 17 16 15 – 14 13 12 11 C7 10 9 8 7 – 6 5 4 3 C6 2 1 0 • C6: Color Space Conversion Matrix Coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875.
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44.5.10 ISI Control Register Name: ISI_CR Address: 0xF8048024 Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 ISI_CDC 7 – 6 – 5 – 4 – 3 – 2 ISI_SRST 1 ISI_DIS 0 ISI_EN • ISI_EN: ISI Module Enable Request Write one to this field to enable the module. Software must poll ENABLE field in the ISI_STATUS register to verify that the command has successfully completed.
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44.5.11 ISI Status Register Name: ISI_SR Address: 0xF8048028 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 SIP 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 CDC_PND 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 ENABLE • ENABLE (this bit is a status bit) 0: Module is disabled. 1: Module is enabled.
PAGE 975
• P_OVR: Preview Datapath Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. This flag is reset after a read operation. • C_OVR: Codec Datapath Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO.
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44.5.
PAGE 977
44.5.
PAGE 978
44.5.14 ISI Interrupt Mask Register Name: ISI_IMR Address: 0xF8048034 Access: Read-write Reset: 0x0 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 – 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 – • DIS_DONE: Module Disable Operation Completed 0: The disable completed interrupt is disabled. 1: The disable completed interrupt is enabled.
PAGE 979
• CRC_ERR: CRC Synchronization Error 0: The crc error interrupt is disabled. 1: The crc error interrupt is enabled. • FR_OVR: Frame Rate Overrun 0: The frame overrun interrupt is disabled. 1: The frame overrun interrupt is enabled.
PAGE 980
44.5.15 DMA Channel Enable Register Name: ISI_DMA_CHER Address: 0xF8048038 Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_EN 0 P_CH_EN • P_CH_EN: Preview Channel Enable Write one to this field to enable the preview DMA channel. • C_CH_EN: Codec Channel Enable Write one to this field to enable the codec DMA channel.
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44.5.16 DMA Channel Disable Register Name: ISI_DMA_CHDR Address: 0xF804803C Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_DIS 0 P_CH_DIS • P_CH_DIS Write one to this field to disable the channel. Poll P_CH_S in DMA_CHSR to verify that the preview channel status has been successfully modified.
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44.5.17 DMA Channel Status Register Name: ISI_DMA_CHSR Address: 0xF8048040 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_S 0 P_CH_S • P_CH_S: 0: Indicates that the Preview DMA channel is disabled 1: Indicates that the Preview DMA channel is enabled. • C_CH_S: 0: Indicates that the Codec DMA channel is disabled.
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44.5.18 DMA Preview Base Address Register Name: ISI_DMA_P_ADDR Address: 0xF8048044 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – P_ADDR 23 22 21 20 P_ADDR 15 14 13 12 P_ADDR 7 6 5 4 P_ADDR • P_ADDR: Preview Image Base Address. (This address is word aligned.
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44.5.19 DMA Preview Control Register Name: ISI_DMA_P_CTRL Address: 0xF8048048 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 P_DONE 2 P_IEN 1 P_WB 0 P_FETCH • P_FETCH: Descriptor Fetch Control Field 0: Preview channel fetch operation is disabled. 1: Preview channel fetch operation is enabled.
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44.5.20 DMA Preview Descriptor Address Register Name: ISI_DMA_P_DSCR Address: 0xF804804C Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – P_DSCR 23 22 21 20 P_DSCR 15 14 13 12 P_DSCR 7 6 5 4 P_DSCR • P_DSCR: Preview Descriptor Base Address (This address is word aligned.
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44.5.21 DMA Codec Base Address Register Name: ISI_DMA_C_ADDR Address: 0xF8048050 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – C_ADDR 23 22 21 20 C_ADDR 15 14 13 12 C_ADDR 7 6 5 4 C_ADDR • C_ADDR: Codec Image Base Address (This address is word aligned.
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44.5.22 DMA Codec Control Register Name: ISI_DMA_C_CTRL Address: 0xF8048054 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 C_DONE 2 C_IEN 1 C_WB 0 C_FETCH • C_FETCH: Descriptor Fetch Control Field 0: Codec channel fetch operation is disabled. 1: Codec channel fetch operation is enabled.
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44.5.23 DMA Codec Descriptor Address Register Name: ISI_DMA_C_DSCR Address: 0xF8048058 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – C_DSCR 23 22 21 20 C_DSCR 15 14 13 12 C_DSCR 7 6 5 4 C_DSCR • C_DSCR: Codec Descriptor Base Address (This address is word aligned.
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44.5.24 ISI Write Protection Control Name: ISI_WPCR Address: 0xF80480E4 Access: Read-write 31 30 29 28 27 WP_KEY (0x49 => “I”) 26 25 24 23 22 21 20 19 WP_KEY (0x53 => “S”) 18 17 16 15 14 13 12 11 WP_KEY (0x49 => “I”) 10 9 8 7 6 5 2 1 0 WP_EN 4 3 • WP_EN: Write Protection Enable 0 = Disables the Write Protection if WP_KEY corresponds. 1 = Enables the Write Protection if WP_KEY corresponds.
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44.5.25 ISI Write Protection Status Name: ISI_WPSR Address: 0xF80480E8 Access: Read-write 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 - 24 - 19 18 17 16 11 10 9 8 3 2 1 0 WP_VSRC 15 14 13 12 WP_VSRC 7 - 6 - 5 - 4 - WP_VS • WP_VS: Write Protection Violation Status WP_VS 0 0 0 0 No Write Protection Violation occurred since the last read of this register (WP_SR).
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45. Ethernet MAC 10/100 (EMAC) 45.1 Description The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal.
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45.3 Block Diagram Figure 45-1.
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45.4 Functional Description The MACB has several clock domains: z System bus clock (AHB and APB): DMA and register blocks z Transmit clock: transmit block z Receive clock: receive and address checker block The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5 MHZ at 10 Mbps). Figure 45-1 illustrates the different blocks of the EMAC module.
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Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (112 bytes) of data. At 100 Mbit/s, it takes 8960 ns to transmit or receive 112 bytes of data. In addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 133 MHz master clock this takes 45 ns, making the bus latency requirement 8915 ns. 45.4.2.
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Table 45-1. Receive Buffer Descriptor Entry (Continued) Bit Function 14 Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame. 13:12 Receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. Updated with the current values of the network configuration register.
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45.4.2.3 Transmit Buffer Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in IEEE Standard 802.3. Zero length buffers are allowed. The maximum number of buffers permitted for each transmit frame is 128.
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Table 45-2. Transmit Buffer Descriptor Entry Bit Function Used. Needs to be zero for the EMAC to read data from the transmit buffer. The EMAC sets this to one for the first buffer of a frame once it has been successfully transmitted. Software has to clear this bit before the buffer can be used again. 31 Note: This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used. 30 Wrap. Marks last descriptor in transmit buffer descriptor list.
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45.4.4 Pause Frame Support The start of an 802.3 pause frame is as follows: Table 45-3. Start of an 802.3 Pause Frame Destination Address Source Address Type (Mac Control Frame) Pause Opcode Pause Time 0x0180C2000001 6 bytes 0x8808 0x0001 2 bytes The network configuration register contains a receive pause enable bit (13).
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group/individual bit: this is One for multicast addresses and Zero for unicast. The All Ones address is the broadcast address, and a special case of multicast. The EMAC supports recognition of four specific addresses. Each specific address requires two registers, specific address register bottom and specific address register top. Specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes.
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hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is, the mul
PAGE 1001
45.4.12 PHY Maintenance The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are configured for the same speed and duplex configuration. The PHY maintenance register is implemented as a shift register.
PAGE 1002
45.5 Programming Interface 45.5.1 Initialization 45.5.1.1 Configuration Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document. To change loop-back mode, the following sequence of operations must be followed: 1. Write to network control register to disable transmit and receive circuits. 2.
PAGE 1003
To create this list of buffers: 1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. 2. Allocate an area 2n words for the transmit buffer descriptor entry in system memory and create N entries in this list. Mark all entries in this list as owned by EMAC, i.e. bit 31 of word 1 set to 0. 3. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit — bit 30 in word 1 set to 1.
PAGE 1004
set. Software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. If there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not available is set.
PAGE 1005
45.6 Ethernet MAC 10/100 (EMAC) User Interface Table 45-7.
PAGE 1006
Table 45-7.
PAGE 1007
45.6.1 Network Control Register Name: EMAC_NCR Address: 0xF802C000 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TE 2 RE 1 LLB 0 LB • LB: LoopBack Asserts the loopback signal to the PHY. • LLB: Loopback Local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with MCK divided by 4.
PAGE 1008
• TSTART: Start Transmission Writing one to this bit starts transmission. • THALT: Transmit Halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
PAGE 1009
45.6.2 Network Configuration Register Name: EMAC_NCFGR Address: 0xF802C004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 IRXFCS 18 EFRHD 17 DRFCS 16 RLCE 14 13 PAE 12 RTY 11 10 9 – 8 BIG 5 NBC 4 CAF 3 JFRAME 2 – 1 FD 0 SPD 15 RBOF 7 UNI 6 MTI CLK • SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin.
PAGE 1010
• CLK: MDC Clock Divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). Value Name Description 0 MCK_8 MCK divided by 8 (MCK up to 20 MHz). 1 MCK_16 MCK divided by 16 (MCK up to 40 MHz). 2 MCK_32 MCK divided by 32 (MCK up to 80 MHz). 3 MCK_64 MCK divided by 64 (MCK up to 160 MHz).
PAGE 1011
45.6.3 Network Status Register Name: EMAC_NSR Address: 0xF802C008 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – • MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. • IDLE 0 = The PHY logic is running. 1 = The PHY management logic is idle (i.e., has completed).
PAGE 1012
45.6.4 Transmit Status Register Name: EMAC_TSR Address: 0xF802C014 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UND 5 COMP 4 BEX 3 TGO 2 RLES 1 COL 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
PAGE 1013
45.6.5 Receive Buffer Queue Pointer Register Name: EMAC_RBQP Address: 0xF802C018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
PAGE 1014
45.6.6 Transmit Buffer Queue Pointer Register Name: EMAC_TBQP Address: 0xF802C01C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
PAGE 1015
45.6.7 Receive Status Register Name: EMAC_RSR Address: 0xF802C020 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 OVR 1 REC 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
PAGE 1016
45.6.8 Interrupt Status Register Name: EMAC_ISR Address: 0xF802C024 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFRE 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLEX 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. • RCOMP: Receive Complete A frame has been stored in memory. Cleared on read.
PAGE 1017
• PTZ: Pause Time Zero Set when the pause time register, 0x38 decrements to zero. Cleared on a read. 45.6.9 Interrupt Enable Register Name: EMAC_IER Address: 0xF802C028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Enable management done interrupt.
PAGE 1018
• PFR: Pause Frame Received Enable pause frame received interrupt. • PTZ: Pause Time Zero Enable pause time zero interrupt.
PAGE 1019
45.6.10 Interrupt Disable Register Name: EMAC_IDR Address: 0xF802C02C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Disable management done interrupt. • RCOMP: Receive Complete Disable receive complete interrupt. • RXUBR: Receive Used Bit Read Disable receive used bit read interrupt.
PAGE 1020
45.6.11 Interrupt Mask Register Name: EMAC_IMR Address: 0xF802C030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Management done interrupt masked. • RCOMP: Receive Complete Receive complete interrupt masked. • RXUBR: Receive Used Bit Read Receive used bit read interrupt masked.
PAGE 1021
45.6.12 PHY Maintenance Register Name: EMAC_MAN Address: 0xF802C034 Access: Read-write 31 30 29 SOF 28 27 26 RW 23 PHYA 22 15 14 21 13 25 24 PHYA 20 REGA 19 18 17 16 CODE 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA • DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. • CODE: Must be written to 10. Reads as written.
PAGE 1022
45.6.13 Pause Time Register Name: EMAC_PTR Address: 0xF802C038 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PTIME 7 6 5 4 PTIME • PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
PAGE 1023
45.6.14 Hash Register Bottom Name: EMAC_HRB Address: 0xF802C090 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Bits 31:0 of the hash address register. See “Hash Addressing” on page 999. 45.6.
PAGE 1024
45.6.16 Specific Address 1 Bottom Register Name: EMAC_SA1B Address: 0xF802C098 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 45.6.
PAGE 1025
45.6.18 Specific Address 2 Bottom Register Name: EMAC_SA2B Address: 0xF802C0A0 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 45.6.
PAGE 1026
45.6.20 Specific Address 3 Bottom Register Name: EMAC_SA3B Address: 0xF802C0A8 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 45.6.
PAGE 1027
45.6.22 Specific Address 4 Bottom Register Name: EMAC_SA4B Address: 0xF802C0B0 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 45.6.
PAGE 1028
45.6.24 Type ID Checking Register Name: EMAC_TID Address: 0xF802C0B8 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID • TID: Type ID checking For use in comparisons with received frames TypeID/Length field.
PAGE 1029
45.6.25 User Input/Output Register Name: EMAC_USRIO Address: 0xF802C0C0 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CLKEN 0 RMII • RMII: Reduce MII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. • CLKEN: Clock Enable When set, this bit enables the transceiver input clock.
PAGE 1030
45.6.26 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers. 45.6.26.
PAGE 1031
45.6.26.3 Single Collision Frames Register Name: EMAC_SCF Address: 0xF802C044 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SCF 7 6 5 4 SCF • SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 45.6.26.
PAGE 1032
45.6.26.5 Frames Received OK Register Name: EMAC_FRO Address: 0xF802C04C Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 FROK 15 14 13 12 FROK 7 6 5 4 FROK • FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory.
PAGE 1033
45.6.26.
PAGE 1034
45.6.26.9 Late Collisions Register Name: EMAC_LCOL Address: 0xF802C05C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 LCOL • LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision. 45.6.26.
PAGE 1035
45.6.26.11 Transmit Underrun Errors Register Name: EMAC_TUND Address: 0xF802C064 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TUND • TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented. 45.6.26.
PAGE 1036
45.6.26.13 Receive Resource Errors Register Name: EMAC_RRE Address: 0xF802C06C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RRE 7 6 5 4 RRE • RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 45.6.26.
PAGE 1037
45.6.26.15 Receive Symbol Errors Register Name: EMAC_RSE Address: 0xF802C074 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RSE • RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception.
PAGE 1038
45.6.26.17 Receive Jabbers Register Name: EMAC_RJA Address: 0xF802C07C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RJB • RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. 45.
PAGE 1039
45.6.26.19 SQE Test Errors Register Name: EMAC_STE Address: 0xF802C084 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SQER • SQER: SQE test errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode.
PAGE 1040
45.6.26.20 Received Length Field Mismatch Register Name: EMAC_RLE Address: 0xF802C088 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RLFM • RLFM: Receive Length Field Mismatch An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field.
PAGE 1041
46. Electrical Characteristics 46.1 Absolute Maximum Ratings Table 46-1. Absolute Maximum Ratings* Operating Temperature (Industrial)...............-40° C to + 85° C Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . ..................................................125°C Storage Temperature................................... -60°C to + 150°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 1042
Table 46-2. DC Characteristics (Continued) VVDDIOP0 DC Supply Peripheral I/Os 1.65 3.6 V VVDDIOP1 DC Supply Peripheral I/Os 1.65 3.6 V VVDDANA DC Supply Analog 3.0 3.6 V VIL Input Low-level Voltage VIH Input High-level Voltage VOL VOH Output High-level Voltage VT- Schmitt trigger Negative going threshold Voltage VT+ Schmitt trigger Positive going threshold Voltage VHYS Schmitt trigger Hysteresis RPULLUP IO VVDDIO from 3.0V to 3.6V -0.3 0.8 V VVDDIO from 1.65V to 1.95V -0.
PAGE 1043
Table 46-2. DC Characteristics (Continued) On VVDDCORE = 1.0V, MCK = 0 Hz, excluding POR All inputs driven TMS, TDI, TCK, NRST = 1 ISC 14 mA TA = 85°C 46 Static Current On VVDDBU = 3.3V, Logic cells consumption, excluding POR All inputs driven WKUP = 0 46.3 TA = 25°C TA = 25°C 8 μA TA = 85°C 18 Power Consumption z Typical power consumption of PLLs, Slow Clock and Main Oscillator. z Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup.
PAGE 1044
Table 46-3. Power Consumption for Different Modes(1) Mode Conditions Consumption Unit ARM Core clock is 400 MHz. MCK is 133 MHz. Active 109 All peripheral clocks activated. mA onto AMP2 Idle state, waiting an interrupt. Idle All peripheral clocks de-activated. 38 mA 8 mA 8 μA onto AMP2 ARM Core clock is 500 Hz. Ultra low power All peripheral clocks de-activated. onto AMP2 Device only VDDBU powered Backup onto AMP1 Table 46-4.
PAGE 1045
46.4 Clock Characteristics 46.4.1 Processor Clock Characteristics Table 46-5. Processor Clock Waveform Parameters Symbol Parameter 1/(tCPPCK) Processor Clock Frequency Conditions VDDCORE = 0.9V T = 85°C Min Max Units 125(1) 400 MHz Min Max Units 125(1) 133 MHz 46.4.2 Master Clock Characteristics Table 46-6. Master Clock Waveform Parameters Symbol Parameter 1/(tCPMCK) Master Clock Frequency Conditions VDDCORE = 0.
PAGE 1046
46.5 Main Oscillator Characteristics Table 46-7.
PAGE 1047
46.5.1 Crystal Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. Table 46-8. Crystal Characteristics Symbol Parameter ESR Equivalent Series Resistor Rs CM Motional Capacitance CS Shunt Capacitance Conditions Min Typ Max @16 MHz 80 @12 MHz CCRYSTAL Max 90 @12 MHz CCRYSTAL Min 110 5 Unit Ω 9 fF 7 pF 46.5.2 XIN Clock Characteristics Table 46-9.
PAGE 1048
46.6 12 MHz RC Oscillator Characteristics Table 46-10. 12 MHz RC Oscillator Characteristics Symbol Parameter F0 Min Typ Max Units Nominal Frequency 8.4 12 15.6 MHz Duty Duty Cycle 45 50 55 % IDD ON Power Consumption Oscillation 86 140 µA 86 125 tON Startup time 6 10 µs IDD STDBY Standby consumption 22 µA 46.7 Conditions 32 kHz Oscillator Characteristics Table 46-11.
PAGE 1049
46.7.1 32 kHz Crystal Characteristics Table 46-12. 32 kHz Crystal Characteristics Symbol Parameter Conditions Min ESR Equivalent Series Resistor Rs Crystal @ 32.768 kHz CM Motional Capacitance Crystal @ 32.768 kHz CS Shunt Capacitance Crystal @ 32.768 kHz Current dissipation Unit 50 100 kΩ 0.6 3 fF 0.6 2 pF CCRYSTAL32 = 6 pF 0.55 1.3 µA (1) CCRYSTAL32 = 12.5pF 0.85 1.6 µA RS = 50 kΩ (1) CCRYSTAL32 = 6 pF 0.7 2.0 µA (1) CCRYSTAL32 = 12.5 pF 1.1 2.2 µA 0.
PAGE 1050
46.8 32 kHz RC Oscillator Characteristics Table 46-14. 32 kHz RC Oscillator Characteristics Symbol Parameter 1/(tCPRCz) Conditions Min Typ Max Unit Crystal Oscillator Frequency 20 32 44 kHz Duty Cycle 45 55 % 75 μs 2.1 µA 0.4 µA Max Unit tST Startup Time IDD ON Power Consumption Oscillation IDD STDBY Standby consumption 46.9 After startup time 1.1 PLL Characteristics Table 46-15.
PAGE 1051
46.9.1 UTMI PLL Characteristics Table 46-17. Phase Lock Loop Characteristics Symbol Parameter FIN Input Frequency FOUT Output Frequency IPLL Current Consumption T Startup Time Conditions Min Typ Max Unit 4 12 32 MHz 450 480 600 MHz 5 8 mA 1.5 µA 50 µs Max Unit active mode standby mode 46.
PAGE 1052
46.11.2 Static Power Consumption Table 46-20. Static Power Consumption Symbol Parameter IBIAS IVDDUTMII IVDDUTMIC Note: Max Unit Bias current consumption on VBG 1 µA HS Transceiver and I/O current consumption 8 µA 3 µA 2 µA Typ Max Unit 0.7 0.8 mA LS / FS Transceiver and I/O current consumption Conditions Min Typ no connection(1) Core, PLL, and Oscillator current consumption 1. If cable is connected add 200 µA (Typical) due to Pull-up/Pull-down current consumption. 46.11.
PAGE 1053
46.12 USB Transceiver Characteristics 46.12.1 Electrical Characteristics Table 46-22. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit 0.8 V Input Levels VIL Low Level VIH High Level VDI Differential Input Sensitivity VCM Differential Input Common Mode Range CIN Transceiver capacitance Capacitance to ground on each line I Hi-Z State Data Line Leakage 0V < VIN < 3.
PAGE 1054
46.13 Analog-to-Digital Converter (ADC) Table 46-24. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency 10-bit resolution mode Startup Time Return from Idle Mode Track and Hold Acquisition Time (TTH) Conversion Time (TCT) Throughput Rate Note: Min ADC Clock = 13.2 MHz (1) ADC Clock = 13.2 MHz (1) ADC Clock = 5 MHz Typ Units 13.2 MHz 40 μs 0.5 μs 1.74 (1) 4.6 ADC Clock = 13.2 MHz(1) ADC Clock = 5 MHz Max 440 (1) 192 µs kSPS 1.
PAGE 1055
Table 46-27. Transfer Characteristics Parameter Min Typ Resolution Max Units 10 bit Integral Non-linearity ±2 LSB ±2 LSB Differential Non-linearity - ADC Clock = 13.2 MHz - ADC Clock = 5 MHz ±0.9 Offset Error ±10 mV - ADC Clock = 13.2 MHz ±3 LSB - ADC Clock = 5 MHz ±2 Gain Error 46.14 Core Power Supply POR Characteristics Symbol Parameter Conditions Min Typ Max Units Vth+ Threshold Voltage Rising Minimum Slope of +2.0V/30ms 0.5 0.7 0.
PAGE 1056
46.14.2 Power-Up Sequence Figure 46-3. VDDCORE and VDDIO Constraints at Startup VDD (V) VDDIO VDDIOtyp VDDIO > Voh Voh VDDIO > Vih Vih VDDCORE VDDCOREtyp Vth+ t <--- Tres ---> < T1 > <------------ T2-----------> Core Supply POR Output SLCK VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach their target values prior to the release of POR.
PAGE 1057
46.15 SMC Timings 46.15.1 Timing Conditions SMC Timings are given for MAX corners. Timings are given assuming a capacitance load on data, control and address pads: Table 46-28. Capacitance Load Corner Supply MAX MIN 3.3V 50pF 5 pF 1.8V 30 pF 5 pF In the following tables, tCPMCK is MCK period. 46.15.2 Timing Extraction 46.15.2.1Zero Hold Mode Restrictions Table 46-29. Zero Hold Mode Use Maximum system clock frequency (MCK) Symbol Parameter Min VDDIOM supply 1.8V Units 3.
PAGE 1058
Table 46-31. SMC Read Signals - NCS Controlled (READ_MODE= 0) Symbol Parameter Min VDDIOM supply Units 1.8V 3.3V NO HOLD SETTINGS (ncs rd hold = 0) SMC8 Data Setup before NCS High SMC9 Data Hold after NCS High 26.9 25.0 ns 0 0 ns 12.3 10.4 ns 0 0 ns (ncs rd setup + ncs rd pulse)* tCPMCK - 18.4 (ncs rd setup + ncs rd pulse)* tCPMCK - 18.
PAGE 1059
Table 46-32. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) (Continued) Symbol Parameter Min 1.8V Supply Max 3.3V Supply 1.8 V Supply 3.3 V Supply Units NO HOLD SETTINGS (nwe hold = 0) SMC21 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25, NCS change(1) 1.9 1.5 SMC21b Min Period/Max Frequency with No Hold settings 11.4 9.7 ns 87 103 ns/ MHz Notes: 1. hold length = total cycle duration - setup duration - pulse duration.
PAGE 1060
Figure 46-4. SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC26 SMC24 A0/A1/NBS[3:0] /A2-A25 SMC13 SMC13 NRD SMC14 NCS SMC14 SMC9 SMC8 SMC10 SMC23 SMC11 SMC22 SMC26 D0 - D15 SMC27 SMC25 NWE NCS Controlled READ with NO HOLD NCS Controlled READ with HOLD NCS Controlled WRITE Figure 46-5.
PAGE 1061
46.16 DDRSDRC Timings The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR modules. DDR2, LP-DDR and SDR timings are specified by the JEDEC standard. Supported speed grade limitations: z DDR2-400 limited at 133 MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#) z LP-DDR limited at 133 MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK) z SDR-100 (3.3V, 50pF on data/control, 10pF on CK) z SDR-133 (3.
PAGE 1062
46.17.1.3 Timing Extraction Figure 46-6. SPI Master mode 1 and 2 SPCK SPI1 SPI0 MISO SPI2 MOSI Figure 46-7. SPI Master mode 0 and 3 SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 46-8.
PAGE 1063
Figure 46-9. SPI Slave mode 1 and 2 NPCS0 SPI13 SPI12 SPCK SPI9 MISO SPI10 SPI11 MOSI Figure 46-10.SPI Slave mode - NPCS timings SPI15 SPI14 SPI6 SPCK (CPOL = 0) SPI12 SPI13 SPI9 SPCK (CPOL = 1) SPI16 MISO Table 46-35. SPI Timings with 3.3V Peripheral Supply Symbol Parameter Cond Min Max Units 66 MHz Master Mode SPISPCK SPI Clock SPI0 MISO Setup time before SPCK rises SPI1 13.
PAGE 1064
Table 46-35. SPI Timings with 3.3V Peripheral Supply (Continued) Symbol Parameter Cond Min Max Units SPI7 MOSI Setup time before SPCK rises SPI8 MOSI Hold time after SPCK rises SPI9 SPCK rising to MISO 2.7 SPI10 MOSI Setup time before SPCK falls 1.7 ns SPI11 MOSI Hold time after SPCK falls 0 ns SPI12 NPCS0 setup to SPCK rising 3.8 ns SPI13 NPCS0 hold after SPCK falling 0 ns SPI14 NPCS0 setup to SPCK falling 3.
PAGE 1065
Figure 46-11.Min and Max access time for SPI output signal SPCK SPI1 SPI0 MISO SPI2max MOSI SPI2min 46.17.2 SSC 46.17.2.1 Timing conditions Timings are given assuming a capacitance load on Table 46-37. Table 46-37. Capacitance Load Corner Supply MAX MIN 3.3V 30pF 5 pF 1.8V 20pF 5 pF 46.17.2.2 Timing Extraction Figure 46-12.
PAGE 1066
Figure 46-13.SSC Transmitter, TK in input and TF in output TK (CKI =0) TK (CKI =1) SSC1 TF/TD Figure 46-14.SSC Transmitter, TK in output and TF in input TK (CKI=0) TK (CKI=1) SSC2 SSC3 TF SSC4 TD Figure 46-15.
PAGE 1067
Figure 46-16.SSC Receiver RK and RF in input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 46-17.SSC Receiver, RK in input and RF in output RK (CKI=1) RK (CKI=0) SSC8 SSC9 RD SSC10 RF Figure 46-18.
PAGE 1068
Figure 46-19.SSC Receiver, RK in ouput and RF in input RK (CKI=0) RK (CKI=1) SSC12 SSC11 RF/RD Table 46-38. SSC Timings Symbol Parameter Cond Min Max 1.8V domain(3) -5.6 5.8 (4) 3.3V domain -4.6 4.9 1.8V domain(3) 3.0 15.7 (4) 3.3V domain 2.3 11.4 1.8V domain(3) 14.0 3.3V domain(4) 9.9 1.8V domain(3) 0 3.3V domain(4) 0 1.8V domain(3) -5.6 (+2*tCPMCK)(1)(4) 5.7 (+2*tCPMCK)(1)(4) (4) (1)(4) 4.
PAGE 1069
Table 46-38. SSC Timings (Continued) Symbol Parameter Cond SSC11 RF/RD setup time before RK edge (RK output) SSC12 RF/RD hold time after RK edge (RK output) SSC13 RK edge to RF (RK output) Min Max (3) 14.1 - tCPMCK (4) 10.0 - tCPMCK 1.8V domain 3.3V domain 1.8V domain(3) tCPMCK - 2.5 (4) tCPMCK - 1.8 3.3V domain ns ns 1.8V domain(3) -5.9 5.2 (4) -4.9 4.3 3.3V domain Units ns Notes: 1. Timings SSC4 and SSC7 depend on the start condition.
PAGE 1070
46.17.3.2 Timing Extraction Figure 46-21.ISI Timing Diagram PIXCLK 3 DATA[7:0] VSYNC HSYNC Valid Data 1 Valid Data Valid Data 2 Table 46-40. ISI Timings with Peripheral Supply 3.3V Symbol Parameter Min Max Units ISI1 DATA/VSYNC/HSYNC setup time TPIXCLK/2 + 0.3 ns ISI2 DATA/VSYNC/HSYNC hold time -TPIXCLK/2 - 3.4 ns ISI3 PIXCLK frequency 54 MHz MHz Max Units Table 46-41. ISI Timings with Peripheral Supply 1.8V Symbol Parameter Min ISI1 DATA/VSYNC/HSYNC setup time TPIXCLK/2 + 0.
PAGE 1071
46.17.5.2 Timing constraints Table 46-43. EMAC Signals Relative to EMDC Symbol Parameter Min (ns) EMAC1 Setup for EMDIO from EMDC rising 10 ns EMAC2 Hold for EMDIO from EMDC rising 10 ns EMAC3 EMDIO toggling from EMDC rising 0 ns(1) Max (ns) 300 ns(1) Notes: 1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC rising edge and the signal change. The Max access timing is the time between the EDMC rising edge and the signal stabilizes.
PAGE 1072
Figure 46-23.
PAGE 1073
46.17.6 USART in SPI Mode Timings 46.17.6.1 Timing conditions Timings are given assuming a capacitance load on Table 46-37. Table 46-45. Capacitance Load Corner Supply MAX MIN 3.3V 40pF 5 pF 1.8V 20pF 5 pF 46.17.6.2 Timing extraction Figure 46-24.USART SPI Master Mode NSS SPI5 SPI3 CPOL=1 SPI0 SCK CPOL=0 SPI4 MISO SPI4 SPI1 SPI2 LSB MSB MOSI Figure 46-25.
PAGE 1074
Figure 46-26.USART SPI Slave mode: (Mode 0 or 3) NSS SPI14 SPI15 SCK SPI9 MISO SPI10 SPI11 MOSI Table 46-46. USART SPI Timings Symbol Parameter Conditions Min Max Units Master Mode SPI0 SCK Period SPI1 Input Data Setup Time SPI2 Input Data Hold Time SPI3 Chip Select Active to Serial Clock SPI4 Output Data Setup Time SPI5 Serial Clock to Chip Select Inactive 1.8v domain(1) 3.3v domain(2) MCK/6 ns 1.8v domain(1) 0.5 * MCK + 4.1 (2) 0.5 * MCK + 3.8 1.8v domain(1) 1.
PAGE 1075
Table 46-46. USART SPI Timings (Continued) Symbol Parameter SPI10 MOSI Setup time before SCK falls SPI11 MOSI Hold time after SCK falls SPI12 NPCS0 setup to SCK rising SPI13 NPCS0 hold after SCK falling SPI14 NPCS0 setup to SCK falling SPI15 NPCS0 hold after SCK rising Conditions Min Max 1.8v domain (1) 2 * MCK + 2.9 3.3v domain (2) 2 * MCK + 2.8 1.8v domain(1) 2.1 (2) 1.8 3.3v domain 2.5 * MCK + 1.4 (2) 2.5 * MCK + 1.2 1.8v domain(1) 1.5 * MCK + 2.5 (2) 1.5 * MCK + 2.2 1.
PAGE 1076
47. Mechanical Overview 47.1 217-ball BGA Package Figure 47-1.
PAGE 1077
Table 47-1. Device and 217-ball BGA Package Maximum Weight 450 mg Table 47-2. 217-ball BGA Package Characteristics Moisture Sensitivity Level 3 Table 47-3. Package Reference JEDEC Drawing Reference MO-205 JESD97 Classification e1 Table 47-4. Package Information Ball Land 0.43 mm ± 0.05 Solder Mask Opening 0.30 mm ± 0.
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47.2 247-ball BGA Packages 47.2.1 247-ball TFBGA package Figure 47-2.
PAGE 1079
Table 47-5. Ball Information Ball pitch 0.5 mm +/- 0.05 Ball Diameter 0.3 mm +/- 0.05 Table 47-6. Package Information Ball Land 0.35 mm +/- 0.05 Solder Mask Opening 0.27 mm +/- 0.05 Table 47-7. Device and 247-ball BGA Package Maximum Weight 177 mg Table 47-8. 247-ball BGA Package Characteristics Moisture Sensitivity Level 3 Table 47-9.
PAGE 1080
47.2.2 247-ball VFBGA package Figure 47-3.
PAGE 1081
Table 47-10. Ball Information Ball Pitch 0.5 mm +/- 0.05 Ball Diameter 0.3 mm +/- 0.05 Table 47-11. Package Information BGA Substrate Ball Land 0.25 mm +/- 0.05 Solder Mask Opening 0.275 mm +/- 0.05 Table 47-12. Device and 247-ball BGA Package Maximum Weight 177 mg Table 47-13. 247-ball BGA Package Characteristics Moisture Sensitivity Level 3 Table 47-14. Package Reference JEDEC Drawing Reference none JESD97 Classification e8 47.
PAGE 1082
48. SAM9G25 Ordering Information Table 48-1.
PAGE 1083
49. SAM9G25 Errata 49.1 External Bus Interface (EBI) 49.1.1 EBI: Data lines are Hi-Z after reset Data lines are Hi-Z after reset. This does not affect boot capabilities neither on NOR nor on NAND memories. Problem Fix/Workaround None. 49.2 Reset Controller (RSTC) 49.2.1 RSTC: Reset during SDRAM Accesses When a Reset (user reset, watchdog, software reset) occurs during SDRAM read access, the SDRAM clock is turned off while data is ready to be read on the data bus.
PAGE 1084
Problem Fix/Workaround: To prevent a SAM-BA execution issue, the USB device must be connected via a USB Full Speed hub to the PC. At application level, the DLL can be re-initialized in the correct state by toggling the BIASEN bit (high -> low -> high) when resuming from the Suspend mode. The BIASEN bit is located in the CKGR_UCKR register in PMC user interface. The function below can be used to generate the pulse on the bias signal.
PAGE 1085
Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during the document review and approval loop. Doc. Rev. Comments 11032C Change Request Ref. Introduction: Section 1. “Features”, added DBGU in the Peripherals list. rfo Section 8.2 “Peripheral Identifiers”, added data on System Controller Interrupt in Table 8-1 “Peripheral Identifiers”.
PAGE 1086
. Doc. Rev. Comments 11032B Change Request Ref. Introduction: Section 4.5 “247-ball BGA Package Pinout”, Table 4-4 “Pin Description BGA247”: fixed typos (inverted “PD1” and 8071 “VDDCORE” in lines U15 and P17, incorrect data in lines J10 and E10) and added missing references to AD0AD4 channels (lines B5, E5, B’, A1, B3). Section 6.3.3 “DDR2SDR Controller”, replaced LPDDR2 with LPDDR. 8146 Added “Write Protected Registers” in the peripherals list in Section 1. “Features”.
PAGE 1087
Doc. Rev. Comments 11032B Change Request Ref. SHDWC: Removed AMBA references from Section 18.2 “Embedded Characteristics”. rfo Section 18.3 “Block Diagram”, removed redundant Figure 18-2. Sutdown Controller Block Diagram. 8454 GPBR: Section 19.3.1 “General Purpose Backup Register x”, removed ‘x’ from the bitfield names in the SYS_GPBRx register table and in the description below. 7990 SCKC: Section 20.
PAGE 1088
Doc. Rev. Comments 11032B Change Request Ref. EBI: Section 26.5.3.4 “Power supplies”, updated the description and added a paragraph concerning power supply when NFD0_ON_D16=1. 8008 Section 26.5.1 “Hardware Interface”, fixed typos in Table 26-4 “EBI Pins and External Device Connections”: the power supply of A20, A23, A24, A25, NCS2, NCS4 and NCS5 is VDDNF and not VDDIOM.
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Doc. Rev. Comments 11032B Change Request Ref. Section 31.7.2 “DMAC Enable Register”, Section 31.7.15 “DMAC Channel x [x = 0..7] Descriptor Address rfo Register”, Section 31.7.16 “DMAC Channel x [x = 0..7] Control A Register”, and Section 31.7.17 “DMAC Channel x [x = 0..
PAGE 1090
Doc. Rev. Comments 11032B Change Request Ref. HSMCI: Section 34.14.12 “HSMCI Status Register”, removed the first phrase in the “NOTBUSY: HSMCI Not Busy” bitfield 8394 description (not only for Write operations now). Section 34.6.3 “Interrupt”, replaced references to NVIC/AIC with “interrupt controller”. 8431 Section 34.14.7 “HSMCI Block Register”, replaced BCNT bitfield table with the corresponding description and updated Warning note in “BCNT: MMC/SDIO Block Count - SDIO Byte Count”. Section 34.14.
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Doc. Rev. Comments 11032B Change Request Ref. USART: Section 39.7.3.4 “Manchester Decoder”, added a paragraph “In order to increase the compatibility...”. 8012 Section 39.8 “Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface”: -updated the reset value of the US_MAN register from ‘0x30011004’ to ‘0xB0011004’ in Table 39-17 “Register Mapping” - updated descriptions of US_CR, US_MR, US_IER, US_IDR, US_IMR, and US_CSR registers in: Section 39.8.
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Doc. Rev. Comments 11032B Change Request Ref. ADC: Section 40.7.15 “ADC Compare Window Register”, added two paragraphs about programming LOWTHRES and 8045 HIGHTHRES bitfields depending on the LOWRES bitfield settings (ADC Mode Register). Section 40.6.4 “Conversion Results”, removed “...and EOC bit corresponding to the last converted channel” from 8357 the last phrase of the third paragraph. Section 40.2 “Embedded Characteristics”, added the value of Conversion Rate in the 2nd line. 8385 SSC: Section 43.
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Doc. Rev. Comments 11032A Change Request Ref.
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Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . .
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11. Boot Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.1 11.2 11.3 11.4 11.5 ROM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Boot . . . . . . . . . . . . . . . . . . . .
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18. Shutdown Controller (SHDWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 18.1 18.2 18.3 18.4 18.5 18.6 18.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . .
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24. Debug Unit (DBGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 24.1 24.2 24.3 24.4 24.5 24.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . .
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29.11 29.12 29.13 29.14 29.15 29.16 Data Float Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable IO Delays . . . . . . . . . . . . . . . .
PAGE 1099
34.10 34.11 34.12 34.13 34.14 CE-ATA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSMCI Boot Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSMCI Transfer Done Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Speed MultiMedia Card Interface (HSMCI) User Interface . . . . . . . . .
PAGE 1100
39.3 39.4 39.5 39.6 39.7 39.8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . .
PAGE 1101
45.4 45.5 45.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993 Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 Ethernet MAC 10/100 (EMAC) User Interface . . . . . . . . . . . . . . . . . . . . . . 1005 46. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 46.1 46.2 46.3 46.4 46.5 46.6 46.7 46.8 46.9 46.10 46.11 46.12 46.13 46.14 46.15 46.16 46.
PAGE 1102
Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Road D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.