Datasheet

11
SAM9G25 [DATASHEET]
11032BS–ATARM–09-Jul-13
4.3 I/O Description
When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the Pin Description table.
Table 4-1. SAM9G25 I/O Type Description
I/O Type Voltage Range Analog Pull-up Pull-down Schmitt Trigger
GPIO 1.65-3.6V Switchable Switchable Switchable
GPIO_CLK 1.65-3.6V Switchable Switchable Switchable
GPIO_CLK2 1.65-3.6V Switchable Switchable Switchable
GPIO_ANA 3.0-3.6V I Switchable Switchable
EBI
1.65-1.95V, 3.0-
3.6V
Switchable Switchable
EBI_O
1.65-1.95V, 3.0-
3.6V
Reset State Reset State
EBI_CLK
1.65-1.95V, 3.0-
3.6V
RSTJTAG 3.0-3.6V Reset State Reset State Reset State
SYSC 1.65-3.6V Reset State Reset State Reset State
VBG 0.9-1.1V I
USBFS 3.0-3.6V I/O
USBHS 3.0-3.6V I/O
CLOCK 1.65-3.6V I/O
DIB 3.0-3.6V I/O
Table 4-2. SAM9G25 I/O Type Assignment and Frequency
I/O Type
I/O Frequency
(MHz)
Charge Load
(pF)
Output
Current
Signal Name
GPIO 40 10 All PIO lines except the following
GPIO_CLK 54 10
MCI0CK, MCI1CK, SPI0SPCK, SPI1SPCK, EMACx_ETXCK,
ISI_MCK
GPIO_CLK2 75 10
GPIO_ANA 25 10
16 mA,
40 mA (peak)
ADx, GPADx
EBI 133
50 (3.3V)
30 (1.8V)
All data lines (Input/output) except the following
EBI_O 66
50 (3.3V)
30 (1.8V)
All address and control lines (output only) except the following
EBI_CLK 133 10 CK, #CK
RSTJTAG 10 10 NRST, NTRST, BMS, TCK, TDI, TMS, TDO, RTCK
SYSC 0.25 10 WKUP, SHDN, JTAGSEL, TST, SHDN
VBG 0.25 10 VBG
USBFS 12 10
HFSDPA, HFSDPB/DFSDP, HFSDPC, HFSDMA,
HFSDMB/DFSDM, HFSDMC
USBHS 480 10 HHSDPA, HHSDPB/DHSDP, HHSDMA, HHSDMB/DHSDM
CLOCK 50 50 XIN, XOUT, XIN32, XOUT32
DIB 25 25 DIBN, DIBP