AT91SAM9G20-EK Evaluation Board ....................................................................................................................
1-2 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide
Table of Contents Section 1 Overview .................................................................................................................... 1-1 1.1 Scope................................................................................................................................. 1-1 1.2 Deliverables ....................................................................................................................... 1-1 1.3 AT91SAM9G20-EK Evaluation Board .............................
Table of Contents (Continued) 4.3 Microcontroller Clock ......................................................................................................... 4-2 4.4 Memory .............................................................................................................................. 4-2 4.5 Ethernet ............................................................................................................................. 4-3 4.6 Miscellaneous ...................................
Section 1 Overview 1.1 Scope The AT91SAM9G20-EK Evaluation Kit enables the evaluation of and code development for applications running on an AT91SAM9G20 device. This guide focuses on the AT91SAM9G20-EK board as an evaluation platform. The board supports the AT91SAM9G20 in a 217-ball LFBGA RoHS-compliant Package. 1.2 Deliverables The AT91SAM9G20-EK package contains the following items: 1.
Overview two user-input push buttons one Wakeup-input push button one reset push button two DataFlash SD/MMC card slots four expansion connectors (PIOA, PIOB, PIOC, IMAGE SENSOR) one BGA-like EBI expansion footprint connector one Lithium Coin Cell Battery Retainer for 12 mm cell size 1-2 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide
Section 2 Setting Up the AT91SAM9G20-EK Board 2.1 Electrostatic Warning The AT91SAM9G20-EK evaluation board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element. 2.
C4 J2 C2 MN1 J16 J19 C3 C1 R70 R71 R77 R78 J3 R10 DS1 R81 R84 R25 C110 C111 C112 C113 R5 R7 K C11 J11 D1 C12 R163 R164 MN10 MN15 Q1 BP2 MN3 R11 R169 R9 Q2 C15 C14 R3 BP1 R167 R64 Q3 J28 C85 R168 R46 R156 R155 R47 R42 MN9 C82 J26 C105 5 MN12 C104 S5 R37 J23 1 J33 R158 C107 TP2 MN5 C47 J7 S2 C146 MN2 C16 J10 J9 R151 R150 C17 R15 C42 Y3 J4 BP3 C87 C25 R49 Y2 C99 TP6 TP5 C26 L3 C101 CR1 TP1 R165 R57 DS5 R108 J15 RR6 RR
C134 C135 CR2 J35 R29 R35 R33 R41 R34 S6 R30 R176 R172 C125 R175 RR14 R174 R92 C49 C48 C31 C30 RR16 C39 C36 C22 S4 R59 C51 C50 RR18 C38 R27 C21 C27 C28 R60 R121 R134 C98 R51 R122 C37 RR9 C33 C46 MN11 R52 R54 C45 R130 C40 C43 RR8 R132 RR7 R118 C32 C44 S7 R133 C91 C92 R53 R58 C96 R61 R126 C88 C89 R65 R137 R24 R23 R109 R125 Y4 R136 R48 C139 C137 C18 C143 C142 R2 R128 C136 R12 L1 C145 C140 R68 R8 R6 R75 R72 R73 J13 C131 C132 R1
Setting Up the AT91SAM9G20-EK Board 2.4 Powering Up the Board The AT91SAM9G20-EK requires 5V DC (±5%). DC power is supplied to the board via the 2.1 mm by 5.5 mm socket J1. Coaxial plug center positive standard. 2.5 Backup Power Supply The user can plug in a battery (3V Lithium Battery CR1225 or equivalent) in order to permanently power the backup part of the device. In this case, J10 configuration must be set in position 1, 2. Refer to Section 4.1 ”Jumpers”. 2.
Setting Up the AT91SAM9G20-EK Board AT91SAM9G20-EK Block Diagram 2.7 AT91SAM9G20-EK Block Diagram Figure 2-3.
Setting Up the AT91SAM9G20-EK Board 2-6 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide
Section 3 Board Description 3.
Board Description • Power Management Controller (PMC) • • • • • • • • • • • • • • • 3-2 6413C–ATARM–18-Feb-09 – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Com
Board Description • IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins • Required Power Supplies – 0.9V to 1.1V for VDDBU, VDDCORE, VDDPLL – 1.65 to 3.6V for VDDOSC – 1.65V to 3.6V for VDDIOP (Peripheral I/Os) – 3.0V to 3.6V for VDDUSB – 3.0V to 3.6V VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or 3.0V to 3.
PIT RSTC SHDC RTT 4GPREG MCI PDC POR VDDCORE NRST POR OSC RC WDT OSC PLLB PLLA PMC PDC DBGU AIC System Controller SLAVE SHDN WKUP VDDBU OSCSEL XIN32 XOUT32 XIN XOUT DRXD DTXD PCK0-PCK1 FIQ IRQ0-IRQ2 TST Filter Filter M C D B0 -M CD M M B3 C C D A0 CD M B C M DA CC 3 D M A CC K 3-4 TWI PDC PIOA PIOC PIOB PDC USART0 USART1 USART2 USART3 USART4 USART5 TD TDI TMO T S C RTK CK JT AG SE L MMU TC0 TC1 TC2 Fast SRAM 16 Kbytes Bus Interface PDC SPI0 SPI1 ROM 64 Kbytes I I
Board Description 3.3 Microcontroller 3.4 3.5 3.6 3.7 3.8 3.9 One 217-ball LFBGA fitted on board Memory 32 Kbytes of Internal ROM Two 4-KByte Internal SRAMs Atmel serial DataFlash 64 Mbytes of SDRAM memory (32-bit bus width) 256 Mbytes of NAND Flash memory (8-bit bus width) TWI serial EEPROM Clock Circuitry 18.
Board Description 3.10 3.11 3.12 3.13 One Ethernet 100-base TX with three status LEDs Audio Stereo Interface Stereo Audio Codec with Integrated Headphone Driver (50 mW on 16W @ 3.
Board Description 3.14 PIO Usage Table 3-1. I/O Peripheral Controller A I/O Line Peripheral A Peripheral B Comments Function PA0 SPI0_MISO MCDB0 SPI DataFlash, SPI/MCI SD/MMC/DataFlash Slot PA1 SPI0_MOSI MCCDB (PA0..
Board Description Table 3-2.
Board Description Table 3-3.
Board Description 3-10 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide
Section 4 Configuration 4.1 Jumpers Table 4-1. Jumpers Configuration Designation Default Setting Feature J2 Closed 3.3V Jumper(1) J3 Closed Forces power on.
Configuration 4.2 JTAG/ICE Table 4-2. JTAG/ICE Configuration Designation 4.3 Default Setting Feature S1 Opened Disables the ICE NTRST input S2 Opened Selects ICE Debug Mode or JTAG Boundary Scan Mode S3 Opened Disables TCK <-> RTCK local loop. If S3 is closed, R13 must be unsoldered. R13 Soldered Enables the ICE RTCK return. S3 must be opened R14 Soldered Enables the ICE RTCK return. S3 must be opened Microcontroller Clock Table 4-3.
Configuration 4.5 Ethernet RMII is the factory default mode. To evaluate the MII mode, the user has to unsolder R49, R50, R127 and close S7 and S8. When the RMII mode is used, the user can use the specific MII signals as PIO, but the following resistors must be unsoldered (R119 to R126). Note that, by default, resistors R112 and R120 are not populated in order to avoid contention between the MII signals and the SD Card slot J35.
Configuration 4-4 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide
Section 5 Schematics 5.
4 3 2 SHEET 3 D[0..31] A[0..22] POWER SUPPLY PB9 5VDC DAC D PB9 PIO SHDN SDCK SDCKE PA23 PA24 PB3 PA23 PA24 PB3 NANDOE NANDW E PA23/TWD PA24/TWCK SPI1_NPCS0 PIO PIO A16 A17 A22 A21 NANDOE NANDWE PC14 PC13 A22 A21 NANDOE NANDW E PC14 PC13 D[0..15] 01 - POWER SUPPLY PB[0..
7 6 5 10 SQUARE CM COPPER AREA FOR HEAT SINKING WITH NO SOLDER MASK MN1 LT1963AEQ-3.
8 7 6 5 4 3 C HDPB HDMB S1 1V0 S2 S3 NTRST H16 R1 T1 L5 C49 100NF P2 C22 100NF U1 C48 4.7µF R18 0R C23 10PF Y1 18.
8 7 6 5 4 3 2 1 SDRAM A[0..14] D[0..31] A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 D A13 23 24 25 26 29 30 31 32 33 34 22 35 SDA10 SDA10 20 21 BA0 BA1 A16 A17 36 40 A14 SDCKE SDCK A0 SDCKE 37 SDCK 38 NBS0 15 39 CFIOR_NBS1_NW R1 CAS RAS 3V3 SDW E R29 470K C R31 SDCS_NCS1 CAS RAS 17 18 SDW E 16 19 MN7 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.
8 7 6 D 5 4 3 2 1 D 3V3 10K 4 C87 100NF C88 22PF SG-8002JC-50.
5 4 3 5V J16 CCUSBA-32002-30X B1 B2 B3 B4 F2 500 mA USB HOST INTERFACE A1 A2 A3 A4 D 1211 109 R66 R67 C110 47pF C111 47pF R70 3V3 DTXD NOT POPULATED DRXD PB14 R74 R76 27R 27R R72 0R R73 0R V+ C2- 11 V- SERIAL DEBUG PORT C105 100NF MALE RIGHT ANGLED C107 100NF 6 1 6 2 7 3 8 4 9 5 RXD TXD 13 R 9 2 7 T 12 15 C104 100NF 14 T 10 HDMB HDPB C113 47pF R77 R75 0R 8 R D J17 R78 R80 100K R82 C 0R PC5 R84 22K 3V3 TXD1 PB6 RTS1 PB28 RXD1 PB7 R87 NOT POPU
8 7 6 5 4 3 2 1 J25 Interposer 100 TOP PA[0..31] PB[0..31] PC[0..
Section 6 Errata 6.1 Wrong Silkscreen of BB and 1.0V on the Board There is a silkscreen reversion on the board, for the selection of the VDDBU source: On J10 position 1-2, the marking should be ‘BB’ for Battery Backup instead of ‘1.0V’ On J10 position 2-3, the marking should be ‘1.0V’ instead of ‘BB’. This erratum is not applicable for AT91SAM9G20-EK Rev. C and later versions. 6.
Errata 6-2 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide
Section 7 Revision History 7.1 Revision History Table 7-1. Document Comments Change Request Ref 6413C Section 6.3 ”SD Card Slots and Booting Capability”, added to errata 6874 6413B Errata section created with Section 6.1 ”Wrong Silkscreen of BB and 1.0V on the Board” 5413 Section 6.2 ”Choice of an Oscillator Capacitance” added to errata 6392 New schematics pdf file (at91sam9g20-ek revc.pdf) attached to Section 5.1 ”Schematics” 5936 - Section 1.
Revision History 7-2 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide
Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.
