Datasheet

892
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
41.7.11 Write Protected Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register
(ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR).
The protected registers are:
z “ADC Mode Register” on page 895
z “ADC Channel Sequence 1 Register” on page 897
z “ADC Channel Sequence 2 Register” on page 898
z “ADC Channel Enable Register” on page 899
z “ADC Channel Disable Register” on page 900
z “ADC Extended Mode Register” on page 909
z “ADC Compare Window Register” on page 910
z “ADC Analog Control Register” on page 912
z “ADC Touchscreen Mode Register” on page 913
z “ADC Trigger Register” on page 918