Datasheet

SAM9G15 [DATASHEET]

11052D–ATARM–31-Oct-12

13.8.6 Spurious Interrupt

The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being

the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is

read. This is most prone to occur when:

z An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time.

z An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded

peripheral is activated for a short time. (As in the case for the Watchdog.)

z An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt

source.

The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When

this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The

programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as

fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from

interrupt.

13.8.7 General Interrupt Mask

The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the

nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this

mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the

processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle

an interrupt. It is strongly recommended to use this mask with caution.

13.9 Write Protection Registers

To prevent any single software error that may corrupt AIC behavior, the registers listed below can be write-protected by

setting the WPEN bit in the AIC Write Protect Mode Register (AIC_WPMR).

If a write access in a write-protected register is detected, then the WPVS flag in the AIC Write Protect Status Register

(AIC_WPSR) is set and the WPVSRC field indicates in which register the write access has been attempted.

The WPVS flag is automatically reset after reading the AIC Write Protect Status Register.