Datasheet

764
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
39.2 Embedded Characteristics
z Programmable Baud Rate Generator
z 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
z 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
z Parity Generation and Error Detection
z Framing Error Detection, Overrun Error Detection
z MSB- or LSB-first
z Optional Break Generation and Detection
z By 8 or by 16 Over-sampling Receiver Frequency
z Optional Hardware Handshaking RTS-CTS
z Receiver Time-out and Transmitter Timeguard
z Optional Multidrop Mode with Address Generation and Detection
z RS485 with Driver Control Signal
z ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
z NACK Handling, Error Counter with Repetition and Iteration Limit
z IrDA Modulation and Demodulation
z Communication at up to 115.2 Kbps
z SPI Mode
z Master or Slave
z Serial Clock Programmable Phase and Polarity
z SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
z LIN Mode
z Compliant with LIN 1.3 and LIN 2.0 specifications
z Master or Slave
z Processing of frames with up to 256 data bytes
z Response Data length can be configurable or defined automatically by the Identifier
z Self synchronization in Slave node configuration
z Automatic processing and verification of the “Synch Break” and the “Synch Field”
z The “Synch Break” is detected even if it is partially superimposed with a data byte
z Automatic Identifier parity calculation/sending and verification
z Parity sending and verification can be disabled
z Automatic Checksum calculation/sending and verification
z Checksum sending and verification can be disabled
z Support both “Classic” and “Enhanced” checksum types
z Full LIN error checking and reporting
z Frame Slot Mode: the Master allocates slots to the scheduled frames automatically.
z Generation of the Wakeup signal
z Test Modes
z Remote Loopback, Local Loopback, Automatic Echo
z Supports Connection of:
z Two DMA Controller Channels (DMAC)
z Offers Buffer Transfer without Processor Intervention