Datasheet

75
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
Figure 13-6. External Interrupt Edge Triggered Source
Figure 13-7. External Interrupt Level Sensitive Source
Figure 13-8. Internal Interrupt Edge Triggered Source
Maximum FIQ Latency = 4 Cycles
Maximum IRQ Latency = 4 Cycles
nFIQ
nIRQ
MCK
IRQ or FIQ
(Positive Edge)
IRQ or FIQ
(Negative Edge)
Maximum IRQ
Latency = 3 Cycles
Maximum FIQ
Latency = 3 cycles
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level)
nIRQ
nFIQ
MCK
nIRQ
Peripheral Interrupt
Becomes Active
Maximum IRQ Latency = 4.5 Cycles