Datasheet

718
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
38.2 Embedded Characteristics
z Three TWIs
z Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices
(1)
z One, Two or Three Bytes for Slave Address
z Sequential Read-write Operations
z Master, Multi-master and Slave Mode Operation
z Bit Rate: Up to 400 Kbits
z General Call Supported in Slave mode
z SMBUS Quick Command Supported in Master Mode
z Connection to DMA Controller (DMA) Channel Capabilities optimizes Data Transfers in Master Mode Only
Note: 1. See Table 38-1 for details on compatibility with I²C Standard.
38.3 List of Abbreviations
Table 38-2. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
PStop
SStart
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
R Read
WWrite