Datasheet

SAM9G15 [DATASHEET]

11052D–ATARM–31-Oct-12

13.2 Embedded Characteristics

z Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM

Processor

z Thirty-two Individually Maskable and Vectored Interrupt Sources

z Source 0 is Reserved for the Fast Interrupt Input (FIQ)

z Source 1 is Reserved for System Peripherals

z Source 2 to Source 31 Control up to Thirty Embedded Peripheral Interrupts or External Interrupts

z Programmable Edge-triggered or Level-sensitive Internal Sources

z Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources

z 8-level Priority Controller

z Drives the Normal Interrupt of the Processor

z Handles Priority of the Interrupt Sources 1 to 31

z Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt

z Vectoring

z Optimizes Interrupt Service Routine Branch and Execution

z One 32-bit Vector Register per Interrupt Source

z Interrupt Vector Register Reads the Corresponding Current Interrupt Vector

z Protect Mode

z Easy Debugging by Preventing Automatic Operations when Protect Models Are Enabled

z Fast Forcing

z Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the Processor

z General Interrupt Mask

z Provides Processor Synchronization on Events Without Triggering an Interrupt

z Write Protected Registers