Datasheet

61
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
Supported Serial Flash Devices
The SPI Flash Boot program supports all SPI Serial Flash devices responding correctly at both Get Status and
Continuous Read commands.
11.4.4.5 TWI EEPROM Boot
The TWI EEPROM Bootloader uses the TWI0. It uses only one valid code detection. It analyzes the ARM exception
vectors.
Supported TWI EEPROM Devices
TWI EEPROM Boot supports all I
2
C-compatible TWI EEPROM memories using 7-bit device address 0x50.
11.4.5 Hardware and Software Constraints
The NVM drivers use several PIOs in peripheral mode to communicate with external memory devices. Care must be
taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time,
and electrical conflicts between output pins used by the NVM drivers and the connected devices may occur.
To assure correct functionality, it is recommended to plug in critical devices to other pins not used by NVM.
Table 11-4 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot
sequence for a period of less than 1 second if no correct boot program is found.
Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program
are set to their reset state.
AT45DB161 16 Mbits 528 4096
AT45DB321 32 Mbits 528 8192
AT45DB642 64 Mbits 1056 8192
Table 11-3. DataFlash Device (Continued)
Device Density Page Size (bytes) Number of Pages
Table 11-4. PIO Driven during Boot Program Execution
NVM Bootloader Peripheral Pin PIO Line
NAND
EBI CS3 SMC NANDOE PIOD0
EBI CS3 SMC NANDWE PIOD1
EBI CS3 SMC NANDCS PIOD4
EBI CS3 SMC NAND ALE A21
EBI CS3 SMC NAND CLE A22
EBI CS3 SMC Cmd/Addr/Data D[16:0]
SD Card
MCI0 MCI0_CK PIOA17
MCI0 MCI0_D0 PIOA15
MCI0 MCI0_D1 PIOA18
MCI0 MCI0_D2 PIOA19
MCI0 MCI0_D3 PIOA20