Datasheet

559
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
32.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)
Name: UDPHS_EPTSTAx [x=0..6]
Access: Read-only
This register view is relevant only if EPT_TYPE=0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register” on page 538
• FRCESTALL: Stall Handshake Request
0 = No effect.
1 = If set a STALL answer will be done to the host for the next handshake.
This bit is reset by hardware upon received SETUP.
• TOGGLESQ_STA: Toggle Sequencing
Toggle Sequencing:
– IN Endpoint: It indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to
the current bank.
– CONTROL and OUT endpoint:
These bits are set by hardware to indicate the PID data of the current bank:
Notes: 1. In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).
2. These bits are updated for OUT transfer:
-
A new data has been written into the current bank.
- The user has just cleared the Received OUT Data bit to switch to the next bank.
3. This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx
(disable endpoint).
• ERR_OVFLW: Overflow Error
This bit is set by hardware when a new too-long packet is received.
Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow
Error bit is set.
This bit is updated at the same time as the BYTE_COUNT field.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
31 30 29 28 27 26 25 24
SHRT_PCKT BYTE_COUNT
23 22 21 20 19 18 17 16
BYTE_COUNT BUSY_BANK_STA CURBK_CTLDIR
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TXRDY TX_COMPLT RXRDY_TXKL ERR_OVFLW
76543210
TOGGLESQ_STAFRCESTALL–––––
Value Name Description
0DATA0 DATA0
1DATA1 DATA1
2 DATA2 Reserved for High Bandwidth Isochronous Endpoint
3 MDATA Reserved for High Bandwidth Isochronous Endpoint