Datasheet

536
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
32.7.7 UDPHS Test Register
Name: UDPHS_TST
Address: 0xF803C0E0
Access: Read-write
• SPEED_CFG: Speed Configuration
Speed Configuration:
• TST_J: Test J Mode
0 = No effect.
1 = Set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line.
• TST_K: Test K Mode
0 = No effect.
1 = Set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line.
• TST_PKT: Test Packet Mode
0 = No effect.
1 = Set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye patterns,
jitter, and any other dynamic waveform specifications.
• OPMODE2: OpMode2
0 = No effect.
1 = Set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI encoding.
Note: For the Test mode, Test_SE0_NAK (see Universal Serial Bus Specification, Revision 2.0: 7.1.20, Test Mode Sup-
port). Force the device in High Speed mode, and configure a bulk-type endpoint. Do not fill this endpoint for sending
NAK to the host.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
– – OPMODE2 TST_PKT TST_K TST_J SPEED_CFG
Value Name Description
0NORMAL
Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host
supports it and then to automatically switch to High Speed mode
1 Reserved
2 HIGH_SPEED
Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug
or test purpose.
3 FULL_SPEED
Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this
configuration, the macro will not respond to a High Speed reset handshake.