Datasheet

512
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
Figure 32-8. NYET Example with Two Endpoint Banks
32.6.10.3Data IN
32.6.10.4Bulk IN or Interrupt IN
Data IN packets are sent by the device during the data or the status stage of a control transfer or during an
(interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or
under the control of the DMA channel.
There are three ways for an application to transfer a buffer in several packets over the USB:
z packet by packet (see 32.6.10.5 below)
z 64 KB (see 32.6.10.5 below)
z DMA (see 32.6.10.6 below)
32.6.10.5Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)
The application can write one or several banks.
A simple algorithm can be used by the application to send packets regardless of the number of banks associated to the
endpoint.
Algorithm Description for Each Packet:
z The application waits for TXRDY flag to be cleared in the UDPHS_EPTSTAx register before it can perform a write
access to the DPR.
z The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window.
z The application sets TXRDY flag in the UDPHS_EPTSETSTAx register.
The application is notified that it is possible to write a new packet to the DPR by the TXRDY interrupt. This interrupt can
be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.
Algorithm Description to Fill Several Packets:
Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application
overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set
by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register.
The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This
means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.
z The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait
that at least one bank is free.
z The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time the
application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS.
z If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the
TXRDY bit in the UDPHS_EPTSETSTAx register.
The application is notified that all banks are free, so that it is possible to write another burst of packets by the
BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the
UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.
t = 0 t = 125 µs t = 250 µs t = 375 µs t = 500 µs t = 625 µs
data 0 ACK data 1 NYET PING ACK data 0 NYET PING NACK PING ACK
Bank 1
Bank 0 Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1E
F
F
E
F
E'
F
E
F
F
E'
F
E
F
E: empty
E': begin to empty
F: full