Datasheet

488
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
31.7.13 DMAC Channel x [x = 0..7] Source Address Register
Name: DMAC_SADDRx [x = 0..7]
Address: 0xFFFFEC3C (0)[0], 0xFFFFEC64 (0)[1], 0xFFFFEC8C (0)[2], 0xFFFFECB4 (0)[3], 0xFFFFECDC (0)[4],
0xFFFFED04 (0)[5], 0xFFFFED2C (0)[6], 0xFFFFED54 (0)[7], 0xFFFFEE3C (1)[0], 0xFFFFEE64 (1)[1],
0xFFFFEE8C (1)[2], 0xFFFFEEB4 (1)[3], 0xFFFFEEDC (1)[4], 0xFFFFEF04 (1)[5], 0xFFFFEF2C (1)[6],
0xFFFFEF54 (1)[7]
Access: Read-write
Reset: 0x00000000
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
• SADDR: Channel x Source Address
This register must be aligned with the source transfer width.
31 30 29 28 27 26 25 24
SADDR
23 22 21 20 19 18 17 16
SADDR
15 14 13 12 11 10 9 8
SADDR
76543210
SADDR