Datasheet

447
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
31. DMA Controller (DMAC)
31.1 Description
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a
destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the
most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from
a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also known
as a dual-access transfer.
The DMAC is programmed via the APB interface.
The DMAC embeds 8 channels.
31.2 Embedded Characteristics
z 2 AHB-Lite Master Interfaces
z DMA Module Supports the Following Transfer Schemes: Peripheral-to-Memory, Memory-to-Peripheral, Peripheral-
to-Peripheral and Memory-to-Memory
z Source and Destination Operate independently on BYTE (8-bit), HALF-WORD (16-bit) and WORD (32-bit)
z Supports Hardware and Software Initiated Transfers
z Supports Multiple Buffer Chaining Operations
z Supports Incrementing/decrementing/fixed Addressing Mode Independently for Source and Destination
z Supports Programmable Address Increment/decrement on User-defined Boundary Condition to Enable Picture-in-
Picture Mode
z Programmable Arbitration Policy, Modified Round Robin and Fixed Priority are Available
z Supports Specified Length and Unspecified Length AMBA AHB Burst Access to Maximize Data Bandwidth
z AMBA APB Interface Used to Program the DMA Controller
z 8 DMA Channels
z 12 External Request Lines
z Embedded FIFO
z Channel Locking and Bus Locking Capability