Datasheet

430
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
30.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface
The User Interface is connected to the APB bus.
The DDRSDRC is programmed using the registers listed in Table 30-16
Table 30-16. Register Mapping
Offset Register Name Access Reset
0x00 DDRSDRC Mode Register DDRSDRC_MR Read-write 0x00000000
0x04 DDRSDRC Refresh Timer Register DDRSDRC_RTR Read-write 0x00000000
0x08 DDRSDRC Configuration Register DDRSDRC_CR Read-write 0x7024
0x0C DDRSDRC Timing Parameter 0 Register DDRSDRC_TPR0 Read-write 0x20227225
0x10 DDRSDRC Timing Parameter 1 Register DDRSDRC_TPR1 Read-write 0x3c80808
0x14 DDRSDRC Timing Parameter 2 Register DDRSDRC_TPR2 Read-write 0x2062
0x18 Reserved – – –
0x1C DDRSDRC Low-power Register DDRSDRC_LPR Read-write 0x10000
0x20 DDRSDRC Memory Device Register DDRSDRC_MD Read-write 0x10
0x24 DDRSDRC DLL Information Register DDRSDRC_DLL Read-only 0x00000001
0x2C DDRSDRC High Speed Register DDRSDRC_HS Read-write 0x0
0x54-0x58 Reserved - - -
0x60-0xE0 Reserved – – –
0xE4 DDRSDRC Write Protect Mode Register DDRSDRC_WPMR Read-write 0x00000000
0xE8 DDRSDRC Write Protect Status Register DDRSDRC_WPSR Read-only 0x00000000