Datasheet

425
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
30.5.6 Write Protected Registers
To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be write-
protected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC Write Protect Status
Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is automatically reset after reading the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR).
Following is a list of the write protected registers:
z “DDRSDRC Mode Register” on page 431
z “DDRSDRC Refresh Timer Register” on page 432
z “DDRSDRC Configuration Register” on page 433
z “DDRSDRC Timing Parameter 0 Register” on page 436
z “DDRSDRC Timing Parameter 1 Register” on page 438
z “DDRSDRC Timing Parameter 2 Register” on page 439
z “DDRSDRC Memory Device Register” on page 442
z “DDRSDRC High Speed Register” on page 444