Datasheet

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SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
30.2 Embedded Characteristics
z AMBA Compliant Interface, interfaces Directly to the ARM Advanced High performance Bus (AHB)
z Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes
Transaction Latency
z AHB Transfer: Word, Half Word, Byte Access
z Supports DDR2-SDRAM, Low-power DDR1-SDRAM, SDR-SDRAM and Low-power SDR-SDRAM
z Numerous Configurations Supported
z 2K, 4K, 8K, 16K Row Address Memory Parts
z SDRAM with Four and Eight Internal Banks
z SDR-SDRAM with 16- or 32-bit Data Path
z DDR-SDRAM with 16-bit Data Path
z One Chip Select for SDRAM Device (256 Mbyte Address Space)
z Programming Facilities
z Multibank Ping-pong Access (up to 4 banks or 8 banks opened at the same time = Reduces Average
Latency of Transactions)
z Timing Parameters Specified by Software
z Automatic Refresh Operation, Refresh Rate is Programmable
z Automatic Update of DS, TCR and PASR Parameters (Low-power SDRAM Devices)
z Energy-saving Capabilities
z Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported
z SDRAM Power-up Initialization by Software
z CAS Latency of 2, 3 Supported
z Reset Function Supported (DDR2-SDRAM)
z ODT (On-die Termination) Not Supported
z Auto Precharge Command Not Used
z SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
z DDR2-SDRAM with Eight Internal Banks Supported
z Linear and Interleaved Decoding Supported
z SDR-SDRAM or Low-power DDR1-SDRAM with 2 Internal Banks Not Supported
z Clock Frequency Change in Precharge Power-down Mode Not Supported
z OCD (Off-chip Driver) Mode Not Supported