Datasheet

35
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
9.4.9 New ARM Instruction Set
AND Logical AND BIC Bit Clear
EOR Logical Exclusive OR ORR Logical (inclusive) OR
MUL Multiply MLA Multiply Accumulate
SMULL Sign Long Multiply UMULL Unsigned Long Multiply
SMLAL
Signed Long Multiply
Accumulate
UMLAL
Unsigned Long Multiply
Accumulate
MSR Move to Status Register MRS Move From Status Register
B Branch BL Branch and Link
BX Branch and Exchange SWI Software Interrupt
LDR Load Word STR Store Word
LDRSH Load Signed Halfword
LDRSB Load Signed Byte
LDRH Load Half Word STRH Store Half Word
LDRB Load Byte STRB Store Byte
LDRBT
Load Register Byte with
Translation
STRBT
Store Register Byte with
Translation
LDRT
Load Register with
Translation
STRT
Store Register with
Translation
LDM Load Multiple STM Store Multiple
SWP Swap Word SWPB Swap Byte
MCR Move To Coprocessor MRC Move From Coprocessor
LDC Load To Coprocessor STC Store From Coprocessor
CDP
Coprocessor Data
Processing
Table 9-2. ARM Instruction Mnemonic List (Continued)
Mnemonic Operation Mnemonic Operation
Table 9-3. New ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
BXJ
Branch and exchange to
Java
MRRC
Move double from
coprocessor
BLX
(1)
Branch, Link and exchange MCR2
Alternative move of ARM reg
to coprocessor
SMLAxy
Signed Multiply Accumulate
16 * 16 bit
MCRR Move double to coprocessor
SMLAL
Signed Multiply Accumulate
Long
CDP2
Alternative Coprocessor
Data Processing
SMLAWy
Signed Multiply Accumulate
32 * 16 bit
BKPT Breakpoint
SMULxy Signed Multiply 16 * 16 bit PLD
Soft Preload, Memory
prepare to load from address
SMULWy Signed Multiply 32 * 16 bit STRD Store Double
QADD Saturated Add STC2
Alternative Store from
Coprocessor