Datasheet

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SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
When handling an ARM exception, the ARM9EJ-S core performs the following operations:
1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode
that has been entered. When the exception entry is from:
z ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15)
+ 4 or PC + 8 depending on the exception).
z THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4
or PC + 8 depending on the exception) that causes the program to resume from the correct place on return.
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on the exception.
4. Forces the PC to fetch the next instruction from the relevant exception vector.
The register r13 is also banked across exception modes to provide each exception handler with private stack pointer.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in the banked LR minus an
offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action
restores both PC and the CPSR.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for
register saving which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a
Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until
the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch
occurs while it is in the pipeline, the abort does not take place.
The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch
Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches
the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the
pipeline, the breakpoint does not take place.
9.4.8 ARM Instruction Set Overview
The ARM instruction set is divided into:
z Branch instructions
z Data processing instructions
z Status register transfer instructions
z Load and Store instructions
z Coprocessor instructions
z Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]).
For further details, see the ARM Technical Reference Manual.
Table 9-2 gives the ARM instruction mnemonic list.
Table 9-2. ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
MOV Move MVN Move Not
ADD Add ADC Add with Carry
SUB Subtract SBC Subtract with Carry
RSB Reverse Subtract RSC Reverse Subtract with Carry
CMP Compare CMN Compare Negated
TST Test TEQ Test Equivalence