Datasheet

33
SAM9G15 [DATASHEET]
11052D–ATARM–31-Oct-12
Figure 9-2. Status Register Format
Figure 9-2 shows the status register format, where:
z N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
z The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD,
QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction
writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.
z The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:
z J = 0: The processor is in ARM or Thumb state, depending on the T bit
z J = 1: The processor is in Jazelle state.
z Mode: five bits to encode the current processor mode
9.4.7.2 Exceptions
Exception Types and Priorities
The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types of
exceptions are:
z Fast interrupt (FIQ)
z Normal interrupt (IRQ)
z Data and Prefetched aborts (Abort)
z Undefined instruction (Undefined)
z Software interrupt and Reset (Supervisor)
When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state.
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the
following priority order:
z Reset (highest priority)
z Data Abort
z FIQ
z IRQ
z Prefetch Abort
z BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time
as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return
from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to
ensure that the transfer error does not escape detection.
Exception Modes and Handling
Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt
from a peripheral.
NZCV Q JIFT
Mode
Reserved
Mode bits
Thumb state bit
FIQ disable
IRQ disable
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
31 30 29 28 27 24 7 6 5 0